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Observer
Observer
11,068 Views
Registered: ‎05-01-2008

FIFO Simulation with QuestaSim

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Hi all,

I am using Vivado 2015.4.1 and QuestaSim 10.4c on Windows 7.

I generated a FIFO using IP Catalog(FIFO Generator v.13) and used in a design, upto this point it was fine, everything is ok. However when I wanted to simulate the FIFO, I got an error like:

 

...Library fifo_generator_v13_0_1 not found.

 

Then I checked the libraries, simulation sources.  The testbench instantiates the fifo from the simulation directory under the generated ip directory(the wrapper), also I added the "fifo_generator_vhdl_beh.vhd" (which the wrapper instantiates) and mapped it to the "fifo_generator_v13_0_1" library.

The wrapper file instantiates a component called fifo_generator_v13_0_1 , but the file fifo_generator_vhdl_beh.vhd does not have one. So, in the hierarchy tab, under simulation sources, the wrapper's sub-module has the "?"  for fifo_generator_v13_0_1.

 

I checked several times, and search on the forums to find what I did wrong or miss, but couldnt find anything.

 

I tried the same flow with Block Memory Generator just to compare the flow, I mean adding simulation files, mapping libraries etc. and it worked with no problem.

 

I wonder if anyone faced such an issue, or have any idea about this ?

 

Sorry, for not posting any piece of code or screenshots, because I couldnt export anything from the machine I use for the project.

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Xilinx Employee
Xilinx Employee
17,769 Views
Registered: ‎09-20-2012

Re: FIFO Simulation with QuestaSim

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Hi @tallman18

 

Edit the _compile.do file to remove testfifo.vhd file and run it manually in questa followed by elaborate.do and simulate.do

 

vcom -64 -93 -work xil_defaultlib ../../../fifosimtest.srcs/sources_1/ip/testfifo/testfifo_sim_netlist.vhdl  ../../../fifosimtest.srcs/sim_1/new/testfifo_tb.vhd 

 

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
11,063 Views
Registered: ‎09-20-2012

Re: FIFO Simulation with QuestaSim

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Hi @tallman18

 

Generate the scripts from Vivado and use them for simulation. Change the simulator to Questasim in simulation settings and use launch_simulation -scripts_only command in TCL console to generate the scripts.

 

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎05-01-2008

Re: FIFO Simulation with QuestaSim

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Hi vemulad, thanks for your quick response. I tried your suggestion but no luck. I got the same error.

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Xilinx Employee
Xilinx Employee
11,017 Views
Registered: ‎09-20-2012

Re: FIFO Simulation with QuestaSim

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Hi @tallman18

 

Is it possible to upload the simulation log files here?

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎05-01-2008

Re: FIFO Simulation with QuestaSim

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Unfortunately, I couldnot export anything from the project PC, however I create the same project with another PC and attached as below. Mahir,
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Xilinx Employee
Xilinx Employee
11,007 Views
Registered: ‎09-20-2012

Re: FIFO Simulation with QuestaSim

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Hi @tallman18

 

I dont see any any attachment in your post, can you upload the file again?

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎05-01-2008

Re: FIFO Simulation with QuestaSim

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Sorry, I am posting again.

 

Mahir,

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Xilinx Employee
Xilinx Employee
10,987 Views
Registered: ‎09-20-2012

Re: FIFO Simulation with QuestaSim

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Hi @tallman18

 

I have generated the IP example design from your XCI file and ran simulation in Questa which went on fine. Can you attach the simulation log of your run?

 

Have you compiled the Xilinx libraries for Questa using compile_simlib?

 

Attaching the log files of my run for your reference.

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎05-01-2008

Re: FIFO Simulation with QuestaSim

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Here the tcl console logs and screen shots. I compiled the simulation libraries and set the path in the simulation settings.

In the compile log of your run there are lots of different files compiled like

testfifo_pkg.vhd

testfifo_rng.vhd

...

I couldnt see them under the fifo's generated files. Do I need to add any library in the testbench, as you can see I didnt add any library in the testbench file other than the standard ones.

 

Mahir,

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Xilinx Employee
Xilinx Employee
10,976 Views
Registered: ‎09-20-2012

Re: FIFO Simulation with QuestaSim

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Hi @tallman18

 

No those files are example design files, you need not compile them.

 

I see below errors in your log file

 

# ** Error: ../../../fifosimtest.srcs/sources_1/ip/testfifo/testfifo_sim_netlist.vhdl(121): (vcom-1484) Unknown formal identifier "IS_CLKARDCLK_INVERTED".

 

It looks like you have not compiled the libraries propertly. In vivado go to Tools --> compile simulation libraries , select simulator, desired output location, sim exec path and click on Compile.

 

Try using these new set of compiled libraries in simulation settings and let us know if you still see the errors.

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎05-01-2008

Re: FIFO Simulation with QuestaSim

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I re-compile the libraries, and try with them, now the log look likes as attached. Complaining about a library that I have already added.

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Xilinx Employee
Xilinx Employee
17,770 Views
Registered: ‎09-20-2012

Re: FIFO Simulation with QuestaSim

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Hi @tallman18

 

Edit the _compile.do file to remove testfifo.vhd file and run it manually in questa followed by elaborate.do and simulate.do

 

vcom -64 -93 -work xil_defaultlib ../../../fifosimtest.srcs/sources_1/ip/testfifo/testfifo_sim_netlist.vhdl  ../../../fifosimtest.srcs/sim_1/new/testfifo_tb.vhd 

 

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎05-01-2008

Re: FIFO Simulation with QuestaSim

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At last :) . Thanks for all your help.

 

By the way, removing the testfifo.vhd from the gui also worked. However it is a little bit confused me because to simulate the fifo, it is said to use the behavioral models under the generated files(testfifo.vhd, fifo_generator_**.vhd).

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