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Visitor tianhufei
Visitor
3,382 Views
Registered: ‎09-12-2016

FIFO generator prog_full and prog_empty assert at the same time.

 I am designing with an async fifo which is 1024 deep having 16bit read and write ports.  I configured the prog_full threshold to be 900, around 90% of the fifo, and prog_empty threshold to be 100 around 10% of the fifo.

 

 During simulation,I can see that prog_empty is asserted ALL the time. Eventhough after 900+ writes performed and prog_full asserted, prog_emtpy is still there high.

 

 Thank you!

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