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Visitor
1,555 Views
Registered: ‎10-13-2017

## FSM does not change state after staying in the same state once

Hi everyone,

I'm implementing a 8 bit unsigned multiplier that uses the add-shift procedure. The code I have while not completely working works when there's a transition of states but doesn't when it needs to stay in the same state. After staying in the same state once, any change of inputs that should result in another change of state does not show up in my simulation. I've looked through my code and I can't figure out why. I seem to have the FSM completely described. Any help or hints would be much appreciated!

```
always@(posedge clk or negedge Start)begin
if(Start)
currentState <= S0;
else
currentState <= nextState;end

always@(*)begin
case (currentState)
S0: if(Start)begin
A[8:0] = 9'b000000000;
B[7:0]  = Mplier;
Counter = 1'd0;
nextState = S1;end
else
nextState <= S0;

S1:  if (K) begin
temp = A[0];
A = A >> 1;
B = B >> 1;
B[7] = temp;
Counter = Counter + 0;
nextState <= S3;end

else if (B[0])begin
A = {Mcand + A[7:0]};
nextState <= S2;end

else begin
temp = A[0];
A = A >> 1;
B = B >> 1;
B[7] = temp;
Counter = Counter + 1;
nextState <= S1;end

S2: if (K) begin
temp = A[0];
A = A >> 1;
B = B >> 1;
B[7] = temp;
Counter = Counter + 0;
nextState <= S3;end
else begin
temp = A[0];
A = A >> 1;
B = B >> 1;
B[7] = temp;
Counter = Counter + 1;
nextState <= S1;end

S3: begin
Counter = 3'b000;
nextState <= S0;end
endcase
end

always@(Counter)begin
if (Counter == 3'b111)
K = 1;
else
K = 0;
end

assign Product = {A, B};
```

So the problem is when B[0] is 0, it should remain in S1 and do a shift. In my testcase, the shift would make B[0] 1 again. This should send my currentState to S2, but it doesn't. I don't know why.

1 Solution

Accepted Solutions
Expert
2,138 Views
Registered: ‎01-23-2009

This is not a state machine (well, it is for the "next_state" but not for anything else).

This is a classic "two process state machine fail".

You have a combinatorial process that updates next_state (which is then clocked in a clocked process), but it also updates a whole bunch of other things like A, B, and counter. Try and think about what the statement "counter <= counter +1" means in this process - this is not a clocked process, hence "counter" is not a flip-flop, so what exactly is "counter"?

You need to rewrite this as a proper 2 process state machine. To do this, you need nextA, nextB and nextCounter, with your clocked process then assigning Counter <= nextCounter; A<=nextA; B<=nextB;

Or (and I strongly prefer this method), rewrite this as a one process state machine, and put everything in your clocked process.

I am not certain that this is what is causing your simulation failure (and I am not going to even try to figure that out - especially since this looks like a homework assignment), but your coding style is incorrect - you need to correctly code in either a 1-process or 2-process state machine style...

Avrum

3 Replies
Expert
2,139 Views
Registered: ‎01-23-2009

This is not a state machine (well, it is for the "next_state" but not for anything else).

This is a classic "two process state machine fail".

You have a combinatorial process that updates next_state (which is then clocked in a clocked process), but it also updates a whole bunch of other things like A, B, and counter. Try and think about what the statement "counter <= counter +1" means in this process - this is not a clocked process, hence "counter" is not a flip-flop, so what exactly is "counter"?

You need to rewrite this as a proper 2 process state machine. To do this, you need nextA, nextB and nextCounter, with your clocked process then assigning Counter <= nextCounter; A<=nextA; B<=nextB;

Or (and I strongly prefer this method), rewrite this as a one process state machine, and put everything in your clocked process.

I am not certain that this is what is causing your simulation failure (and I am not going to even try to figure that out - especially since this looks like a homework assignment), but your coding style is incorrect - you need to correctly code in either a 1-process or 2-process state machine style...

Avrum

Visitor
1,522 Views
Registered: ‎10-13-2017

@avrumw Thanks so much for your help! I did as per your suggestions and the circuit works now.

Do you mind explaining what you exactly mean by "two process state machine fail". Although I managed to get the circuit working now, I still don't understand why my previous method can't work. I can't see what's wrong with it.

Oh ad also, what is the difference between a one process state and two process state?Some links to example would be helpful.

Also, in a FSM implementation, what should or shouldn't go into a combinatorial block? Thanks again!

Expert
1,477 Views
Registered: ‎01-23-2009

My suggestion to you is that you go back to your instructor with these questions (assuming this is school work) and/or get a good book on Verilog coding. These are fundamental questions about how to use the language and how to code RTL...

Avrum