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kimjaewon
Adventurer
Adventurer
3,523 Views
Registered: ‎11-18-2017

Functional vs Timing simulation in VIVADO

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Hello, I'm new in Xilinx Vivado and I have some questions about simulation.

 

I see there are 5 different simulation in Xilinx as below fig. 1.

fig. 1fig. 1

 

So I tried every 5 simulation as below.

 

BehavioralBehavioral

 

Post-Synthesis FunctionalPost-Synthesis Functional

 

Post-Synthesis TimingPost-Synthesis Timing

 

Post-Implementation FunctionalPost-Implementation Functional

 

Post-Implementation TimingPost-Implementation Timing

 

 

 

I can see that Behavioral, Post-Synthesis Functional and Post-Implementation Functional show same results. 

I think this is because behavioral and functional ignores time information (maybe cell, propagate delay or rising/falling/hold time or whatever) and represents only pure logic but I'm not sure about it.

But Post-Synthesis Timing and Post-Implementation Timing looks different. 

They might have 

I guess those two applied timing information but although they both applied it, they look different.

Is is that Post-Synthesis Timing cares only about cell delays but Post-Implementation Timing cares both the cell delays and the routing delays occurred from mapping? It is my estimation so I'm not sure about it.

Additionally, in Post-Implementation Timing, the output(led_out) goes to a wrong value '05' for a very short moment and then returns to the right value '07'. Why does this happened?

 

Thanks for your help.

 ps. I heard that I need to add sdf. file to do the timing simulation but I have never done that.

I think the Vivado automatically added the sdf. file on behalf of me so that the timing simulation could differ from the functional simulation. Am I correct?

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eilert
Teacher
Teacher
3,498 Views
Registered: ‎08-14-2007

Hi,

you assumptions are mostly correct.

For the post synthesis timing simulation:

Since the design is unrouted then, only some statistical information about the routing delay is used. Especially for such a small  test design that will most probably have long routes between the given I/Os the post synthesis simulation will show shorter delays than the post PAR simulation.

About the wrong value seen in the post PAR simulation:

You are looking at  8-Bit busses. The logic between the inputs and outputs is unknown to me, but more than one output line has to change its state. The length of these routes (and maybe the logic depth too) will be different. So you will see intermediate values before all lines have reached their final state. Just expand the busses to take a closer view at the single wires of the bus and you will see that behavior.

 

Yes, an SDF file is needed for timing simulations. Vivado and Xsim handles this automatically. The SDF file can have min. typ. and max. delay informations, that can be selected for viewing. Please take a look at the documentation how to do this.

Also look at the console outputs and log files. There should be some lines of tcl code or scripts that show you how the simulator is started and what options are set. 

 

Have a nice simulation

  Eilert

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2 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
3,508 Views
Registered: ‎05-22-2018

Hi @kimjaewon,

Please check page no.67 of below link for detailed explanation on your queries:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug900-vivado-logic-simulation.pdf

Thanks,

Raj

eilert
Teacher
Teacher
3,499 Views
Registered: ‎08-14-2007

Hi,

you assumptions are mostly correct.

For the post synthesis timing simulation:

Since the design is unrouted then, only some statistical information about the routing delay is used. Especially for such a small  test design that will most probably have long routes between the given I/Os the post synthesis simulation will show shorter delays than the post PAR simulation.

About the wrong value seen in the post PAR simulation:

You are looking at  8-Bit busses. The logic between the inputs and outputs is unknown to me, but more than one output line has to change its state. The length of these routes (and maybe the logic depth too) will be different. So you will see intermediate values before all lines have reached their final state. Just expand the busses to take a closer view at the single wires of the bus and you will see that behavior.

 

Yes, an SDF file is needed for timing simulations. Vivado and Xsim handles this automatically. The SDF file can have min. typ. and max. delay informations, that can be selected for viewing. Please take a look at the documentation how to do this.

Also look at the console outputs and log files. There should be some lines of tcl code or scripts that show you how the simulator is started and what options are set. 

 

Have a nice simulation

  Eilert

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