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Registered: ‎02-17-2010

Gate level of simulation of DCM does not work

I'm running ModelSim PE 6.6, and using ISE 10.1 (it's old, but works). I'm doing a gate level simulation but the DCM simulation is not right. There is a 2.3 ns delay for the clock input to the DCM, which results in the output clock of the DCM and my input clock not being locked. The clock that is being fed is 100 Mhz, so 2.3 ns throws everything out of wack. Has anyone seen this problem and have a work around ? I'm tempted to edit the .sdf file..

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Xilinx Employee
Xilinx Employee
Registered: ‎09-14-2007



Rather than editing the SDF file, I would recommend upgrading to 11.4. There is not enough detail to know if this is a known issue in 10.1, although I remember when in the first release of 10.1 we had a bug in the DCM lock that we fixed in one of the service packs.





Message Edited by duthv on 02-18-2010 02:33 PM
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The Possible reasons for DCM not locking might be due to one of the below 


  • If the input clock is not stable
  • More Jitter in Input clock
  • If the DCM has external feedback, the feedback clock will not be present at the DCM CLKFB pin.
  • GTS is not released during the startup sequence.
  • when  DFS outputs are used and the CLKIN frequency falls outside the specified range
  • If some problem in VCCAUX voltage like noise spike which takes out acceptable operating range specified in data sheet.
  • In case when the reset signals of the DCM and PLL are tied together, the second component in the chain will automatically wait for the first to lock before starting it's own locking cycle.

Also   link helps for debugging


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