UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant kwiatlab
Participant
5,886 Views
Registered: ‎01-19-2012

Having trouble simulating Xilinx primitives.

Hello,

 

I'm having trouble simulating Xilinx primitives using the schematic. I've simplified my design to contain only a flip-flop (the FDC symbol), with D hooked up to Vcc, CLR hooked up to GND, and the clock being an input I control. When the input goes high, I would expect the output to also go high, but this never happens. When I simulate, the output of the flipflop stays low.

 

Now I've noticed that for these symbols when I right click and try and push into symbol, the option is greyed out. Usually, when I go into a symbol included in the Xilinx libraries, I'm linked to the .vhd file. This is not occuring here. I can find the fdc.vhd file in the vhdl/hdlmacro directory of ISE 14.7 .... and I realize I can simply just make my own flip flop, but why aren't these ready-made ones working in simulation?

 

 

0 Kudos
3 Replies
Participant kwiatlab
Participant
5,884 Views
Registered: ‎01-19-2012

Re: Having trouble simulating Xilinx primitives.

Sorry, the fdc.vhd file is located in the path

C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\primitive

 

not hdlmacros.

0 Kudos
Xilinx Employee
Xilinx Employee
5,862 Views
Registered: ‎07-16-2008

Re: Having trouble simulating Xilinx primitives.

The unisim library should be called by default by ISIM. Otherwise the cells in the schematic won't be resolved.

Can you attach the testcase which demonstrates the incorrect simulation result?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Moderator
Moderator
5,853 Views
Registered: ‎04-17-2011

Re: Having trouble simulating Xilinx primitives.

Did you check your testbench to see if the clock is properly generated? Also for the schematic (Push into symbol) issue, feel free to post a new topic in our Design Entry board.
Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos