04-28-2014 12:40 PM
I'm having trouble simulating Xilinx primitives using the schematic. I've simplified my design to contain only a flip-flop (the FDC symbol), with D hooked up to Vcc, CLR hooked up to GND, and the clock being an input I control. When the input goes high, I would expect the output to also go high, but this never happens. When I simulate, the output of the flipflop stays low.
Now I've noticed that for these symbols when I right click and try and push into symbol, the option is greyed out. Usually, when I go into a symbol included in the Xilinx libraries, I'm linked to the .vhd file. This is not occuring here. I can find the fdc.vhd file in the vhdl/hdlmacro directory of ISE 14.7 .... and I realize I can simply just make my own flip flop, but why aren't these ready-made ones working in simulation?
04-28-2014 12:42 PM
Sorry, the fdc.vhd file is located in the path
04-28-2014 06:55 PM
The unisim library should be called by default by ISIM. Otherwise the cells in the schematic won't be resolved.
Can you attach the testcase which demonstrates the incorrect simulation result?
04-28-2014 11:21 PM