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Adventurer
Adventurer
768 Views
Registered: ‎06-25-2015

Help understanding what this error code means

Hello, I am trying to simulate my design and I get this error. The design is a mixture of VHDL and Verilog. I get the following error when trying to simulate.

 

[XSIM 43-3253] File C:/Program Files/Opal Kelly/FrontPanelUSB/FrontPanelHDL/XEM7010-A50/okCoreHarness.v, line 9964. Verilog alias ports are not supported in mixed language simulation.

 

What is this referring to?

 

Thank you

 

Adam

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2 Replies
Moderator
Moderator
767 Views
Registered: ‎09-15-2016

Re: Help understanding what this error code means

@acgropp1

 

Refer the below link for restriction of Mixed language with Vivado simulator:

https://www.xilinx.com/support/answers/64050.html

 

Regards

Rohit

Regards
Rohit
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Moderator
Moderator
717 Views
Registered: ‎04-24-2013

Re: Help understanding what this error code means

Hi @acgropp1,

 

There is a list of what is supported in Mixed Language Simulation in Appendix G of User Guide 900 (attached).

 

Best Regards
Aidan

 

 

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