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Registered: ‎07-30-2019

How do I print (put in a log) signal values in a Tcl script running under ModelSim ME

I need perform the Post-Layout Simulation of my Design by following Manner by using ModelSim:

1. Injecting the Design(VHDL) Entity Inputs.
2. Force the internal Net list signals.
3. Monitor the Internal net outputs.
4. Monitor the Design Outputs.

I am more interested about the scripting the above problem to log all the internal output signals.

If I have only one signal, I can see it and verify. Real time scenario I have multiple signals to monitor,
What is the best way to solve the above problem. What is the best way to log the internal signals based on specific conditions or time.
Below are the sample Input and Outputs of design and its internal signals.

UUT inputs signals

sim:/tb_uut/uut/Port1_Input1
sim:/tb_uut/uut/Port2_Input2

Internal Input and Outputs signals

sim:/tb_uut/uut/Input1_Internal
sim:/tb_uut/uut/Input2_Internal
sim:/tb_uut/uut/Output1_internal
sim:/tb_uut/uut/Output2_internal

UUT Output Signals
sim:/tb_uut/uut/Port3_Output

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