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lis_user1
Explorer
Explorer
12,158 Views
Registered: ‎11-17-2015

How do I probe all signals in a vivado simulation?

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In ncsim I am able to probe all the signals during a simulation without adding to waveforms. 

How do I do the same in Vivado and Modelsim? 

 

 

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dprasad
Xilinx Employee
Xilinx Employee
22,059 Views
Registered: ‎09-13-2014

Once simulation is launched do following on TCL console

 

1> restart -- This is to bring the simulation at time 0

2> log_wave -r *  -- This will log(probe) all signals but won't add in waveform

 

--dhiRAj

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vijayak
Xilinx Employee
Xilinx Employee
12,112 Views
Registered: ‎10-24-2013

Hi @lis_user1

 

Set debug level to all as in the screenshot attached.

Thanks,Vijay
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vijayak
Xilinx Employee
Xilinx Employee
12,064 Views
Registered: ‎10-24-2013

Hi @lis_user1

Did my previous post answered your query?

Thanks,Vijay
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dprasad
Xilinx Employee
Xilinx Employee
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Registered: ‎09-13-2014

Once simulation is launched do following on TCL console

 

1> restart -- This is to bring the simulation at time 0

2> log_wave -r *  -- This will log(probe) all signals but won't add in waveform

 

--dhiRAj

View solution in original post

lis_user1
Explorer
Explorer
12,046 Views
Registered: ‎11-17-2015

Thank you. 

I did both your answer and dprasad's answer. 

Now it works. 

 

Thank you both. 

 

 

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lis_user1
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Explorer
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Registered: ‎11-17-2015
A quick question,

Is tcl commands used in model-sim compatible with the Vivado simulator?
My company uses both, reuseability is nice.

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dprasad
Xilinx Employee
Xilinx Employee
12,027 Views
Registered: ‎09-13-2014
No, it's can't be due to policy.
lis_user1
Explorer
Explorer
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Registered: ‎11-17-2015

I see. I realize I was unable to add a verilog event into the vivado waveform, am I right? 

How do I add a event to waveform? 

 

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srimaye
Xilinx Employee
Xilinx Employee
11,972 Views
Registered: ‎09-25-2014

Hi,

 

Vivado does not support tracing of events in verilog. You can refer pg 43 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug900-vivado-logic-simulation.pdf

 

Thanks,

Srimayee

vijayak
Xilinx Employee
Xilinx Employee
11,968 Views
Registered: ‎10-24-2013

Hi @lis_user1

Please create a new thread for the neq queries. This way it is easier to track.

Thanks,Vijay
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lis_user1
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Registered: ‎11-17-2015
Ok.
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tflekan_ddc
Visitor
Visitor
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Registered: ‎03-01-2021

Hi dprasad,

I'm responding to this message late but I have a related question: how do set up Vivado to probe none of the signals?  I have a regressions simulation where I only care about the text output and a pass or fail.  My intent is to run the simulation as quickly as possible and would like to disable all logging and debug features.  Can you help with this?

 

Ted

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