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Visitor girishs12
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Registered: ‎09-19-2009

How do i invoke a verilog module from vhdl?

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Hi

I want to know what is the type of source i need to declare if i'm doing a mixed language synthesis and i want to invoke a verilog module into vhdl?

I have xilinx 9.1 and i wrote the entire prog that had the vhdl part and below that the verilog module that i wished to invoke. but there was a error msg for the line,the verilog module starts.

Any sol?

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Instructor
Instructor
18,416 Views
Registered: ‎08-14-2007

Re: How do i invoke a verilog module from vhdl?

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What you should do depends on what you need from the Verilog module.

 

Do you really need to change the values of parameters in this module?  If not,

just get rid of the generics.

 

If you need to modify the parameter values, then I would suggest using a Verilog

wrapper to set the parameter values (assuming you can't get the generics working

from VHDL) and then instantiate the wrapper in VHDL.

 

Alternately, if you only need one instance of this Verilog module, you can edit the

Verilog code to set the default value of the parameters to the values you need.

 

- Gabor

-- Gabor
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Instructor
Instructor
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Registered: ‎08-14-2007

Re: How do i invoke a verilog module from vhdl?

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You should keep your Verilog module in a separate source file.  The

parser will only run one language on any file.  Mixed language designs

need separate files.  I would normally place each entity or module

in its own file anyway.  This makes it easier to manage projects

and helps avoid throwing out necessary modules by mistake when

removing another in the same file.

 

If your project is mostly VHDL, you can still add Verilog modules to

it.  The simplest way to instantiate the Verilog module is to use the

ISE nvigator process "view instantiation template" under the processes

for the Verilog module.  This should give you a VHDL instantiation

template, including the component declaration.

 

HTH,

Gabor

-- Gabor
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Visitor nirmalapss
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Registered: ‎05-21-2012

Re: How do i invoke a verilog module from vhdl?

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Hi,

I have invoked verilog file in VHDL project by view instantiation temlate.when i am synthezing i getting errors...in verilog file about parameters declaration/generic

 

ERROR:Xst:2584 - generic <Erase> of instance <U5> has different type in definition <FLASH_IFC>.

Flash_IFC is verilog file.

 

suggest me...

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Instructor
Instructor
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Registered: ‎08-14-2007

Re: How do i invoke a verilog module from vhdl?

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@nirmalapss wrote:

Hi,

I have invoked verilog file in VHDL project by view instantiation temlate.when i am synthezing i getting errors...in verilog file about parameters declaration/generic

 

ERROR:Xst:2584 - generic <Erase> of instance <U5> has different type in definition <FLASH_IFC>.

Flash_IFC is verilog file.

 

suggest me...


In Verilog, parameters default to integer type.  There are some exceptions where the type can

be inferred from the syntax, like reals (ex: parameter foo = 1.07;) or strings (ex: parameter foo = "bar";).

There may be some types that don't directly map into VHDL well.  In those cases you're probably

better off using a Verilog wrapper to instantiate the verilog module along with its parameters,

and then instantiating the wrapper from VHDL without using generics.  If you post code where

the parameter is defined, I might be able to help more.

 

-- Gabor

-- Gabor
Visitor nirmalapss
Visitor
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Registered: ‎05-21-2012

Re: How do i invoke a verilog module from vhdl?

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I AM POSTING THE CODE...VERILOG Wrappers means...i am unable to post full code as characters are limited

 


`
module FLASH_IFC  //Outputs from fpga to external flash

                    (
                    ADDRS_BUS,                        
                    E_bar,                    
                    G_bar,                    
                    W_bar,
                    WP_bar,
                    BYTE_bar,                 
                    RP_bar,
                    FLASH_DATA,
                    DATA_valid,
                    FLASH_ready,
                    init_done,
                    POLLING_bit,
                    TOGGLE_bit,
                    ERROR_bit,
                    ERASE_TIMER_BIT,
                    ALT_TOGGLE_BIT,
                    Ready_done,
                    
                    //Inout
                    
                    DATA_BUS,
                    
                    //Inputs to fpga
                    
                    CLK40MHz,                        
                    RST,                                
                    WR_EN,                            
                    RD_EN,
                    FL_ERASE,
                    ID_RD,
                    ADDRS_IN,                
                    DATA_IN,
                    RB_bar,
                    
                    //Miscellaneous
                    
                    dq
                    );
                
//-------------------------------------------------------------------------------
// INPUTS
//-------------------------------------------------------------------------------
input                CLK40MHz;        // On board clock for synchronization (40MHz).
input                RST;            // External H/W reset pin to FPGA.
input                WR_EN;            // Write enable interrupt for issuing a write command to FLASH.
input                RD_EN;            // Read enable interrupt for issuing a read command to FLASH.
input                FL_ERASE;        // 'FLASH ERASE' (Block/chip erase) interrupt.    
input                ID_RD;            // Device ID, Manufacturer CODE read interrupt.
input    [15:0]        DATA_IN;        // Input data (8 / 16 bit) to be loaded onto the FLASH.
input    [19:0]        ADDRS_IN;        // Input address for data to be loaded.        // Actually 24bit addr from frames
input                RB_bar;            // Ready/Busy pin to indicate an operation in progress in FLASH.    

//-------------------------------------------------------------------------------
// INOUT
//-------------------------------------------------------------------------------
inout    [15:0]        DATA_BUS;        // Bi-directional data bus to load data onto the FLASH.

//-------------------------------------------------------------------------------
// OUTPUTS
//-------------------------------------------------------------------------------
output    [19:0]    ADDRS_BUS;        // Address bus going to the external FLASH.
output            E_bar;            // Chip Enable for the FLASH.
output            G_bar;            // Output Enable for the FLASH.
output            W_bar;            // Write Enable for the FLASH.
output            BYTE_bar;        // Byte/Word Organization Select 0 -> 16 bit mode , 1 -> 8 bit mode.
output            RP_bar;            // Reset/Block Temporary Unprotect pin.
output            WP_bar;            // Write protect
output    [15:0]  FLASH_DATA;        // Data read out from the Flash.
output            DATA_valid;        // Data capture pulse.
output            FLASH_ready;    // Flash Ready/Busy indicating signal.
output            init_done;
output    [15:0]  dq;
output            POLLING_bit;        // Data Polling bit.     //
output            TOGGLE_bit;            // Data Toggle bit.      //
output            ERROR_bit;            // Error flag bit.       // Status Register contents
output            ERASE_TIMER_BIT;    // Erase timer bit.      //
output            ALT_TOGGLE_BIT;        // Alternate toggle bit. //
output            Ready_done;
    

//-------------------------------------------------------------------------------
// OUTPUTS REGISTERED
//-------------------------------------------------------------------------------
    reg            [19:0]    ADDRS_BUS;            //    
    reg                    E_bar;                //
    reg                    G_bar;                //
    reg                    W_bar;                // Registering the outputs (Behavioral style).
    reg                    RP_bar;                //
    reg                    WP_bar;                //
    reg                    BYTE_bar;            //
    reg                    DATA_valid;
    reg                    FLASH_ready;
    reg                    Ready_done;
    
      reg                    init_done;
    reg            [15:0]    dq;
    
    reg                    POLLING_bit;
    reg                    TOGGLE_bit;  
    reg                    ERROR_bit;  
    reg                    ERASE_TIMER_BIT;
    reg                 ALT_TOGGLE_BIT;    

//-------------------------------------------------------------------------------
// PARAMETER DECLARATIONS FOR "STATES" USED IN THE ONE-HOT ENCODED FSM...
//-------------------------------------------------------------------------------
    parameter    [9:0]    IDLE     = 0,        // STATE for deciding states' transitions.
                    DELAY    = 1,        // STATE for calculation of the 'DELAYS'.
                    RESET    = 2,        // STATE for 'RESET' operation on FLASH.
                    READ     = 3,        // STATE for 'READ' interupt operation.
                    WRITE    = 4,        // STATE for 'WRITE' interupt operation.
                    ERASE    = 5,        // STATE for 'FLASH ERASE' operation (block/chip).
                    RD_RST   = 6,        // STATE for 'READ/RESET' operation.
                    STATUS   = 7,        // STATE for 'STATUS REGISTER CHECK'.
                    POLLING  = 8,        // STATE for 'Flash polling flow chart'.
                    AUTO_SEL = 9;        // STATE for 'Reading Manufacturer's code'.

//-------------------------------------------------------------------------------
// PARAMETER DECLARATIONS FOR "DELAYS" IN THE FLASH...
//-------------------------------------------------------------------------------
   // READ parameters..
    parameter    [3:0]    tAVAV  = 9;            // Address Valid to Next Address Valid              ->  90 ns(min)
    parameter            tOE    = 2;            // Output Enable trig to Output Valid              ->  35 ns  "
    parameter    [1:0]    tDLY   = 3;       // Chip Enable trig to Output enable trig          ->  65 ns  "
//    parameter   [1:0]    tCE    = 4;            // Chip Enable trig to Output Valid                ->  90 ns  "
//    parameter   [2:0]     tACC   = 4;            // Address Valid to Output Valid                 ->  90 ns(max)
//    parameter   [1:0]    tHZ    = 2;            // Chip Enable High to Output Hi-Z                     ->  30 ns  "
//    parameter   [1:0]    tDF    = 2;            // Output Enable High to Output Hi-Z               ->  30 ns  "
//    parameter   [1:0]    tFLQZ  = 2;            // BYTE trig to Output Hi-Z                        ->  30 ns  "
//    parameter   [1:0]    tFHQV  = 2;         // BYTE High to Output Valid                       ->  40 ns  "
    
        // WRITE parameters -> write enable controlled..
//    parameter    [2:0]        tWC    = 4;         // Address Valid to Next Address Valid             ->  90 ns(min)
//    parameter   [1:0]        tWP    = 3;         // Write Enable trig to Write Enable High          ->  50 ns  "
//    parameter   [1:0]        tDS    = 3;         // Input Valid to Write Enable High                ->  50 ns  "
//    parameter   [1:0]        tWPH   = 2;         // Write Enable High to Write Enable trig          ->  30 ns  "
//    parameter   [1:0]        tAH    = 3;         // Write Enable trig to Address Transition         ->  50 ns  "
//    parameter   [1:0]     tBUSY  = 2;         // Program/Erase Valid to RB trig                  ->  35 ns(max)

        // WRITE parameters -> chip enable controlled..
    parameter    [2:0]        tCP    = 4;     // Chip Enable trig to Chip Enable High            ->  50 ns(min)
    parameter    [1:0]        tCPH   = 2;     // Chip Enable High to Chip Enable trig           ->  30 ns  "
    parameter    [3:0]        tWCYCL = 12;        // Write cycle.  

        //Reset/Block Temporary Unprotect parameter decl..
    parameter   [5:0]        tRP    = 39;      // RP Pulse Width(1us)                             -> 500 ns  "
    parameter   [8:0]        tREADY = 399;      // RP trig to Read Mode                            ->  10 us(max)
//    parameter   [5:0]        tVIDR  =  41;      // RP Rise Time to VID                             -> 500 ns(min)
//    parameter   [3:0]        tVHVPP =  11;      // VPP Rise and Fall Time                          -> 250 ns  "
//    parameter   [1:0]        tRH    =   3;     // RP High to Wr_En,Chip_En,Output_En trig         ->  50 ns  "

    parameter    [2:0]        tVALID = 5;        // Time during which the DQ is in Write mode..  ->  75 ns(Typ)

//-------------------------------------------------------------------------------
// PARAMETER DECLARATIONS FOR "COMMANDS" USED IN THE ONE-HOT ENCODED FSM...
//-------------------------------------------------------------------------------
    parameter    [3:0]        Nop            = 1;     // No operation command.
    parameter    [3:0]        Reset        = 2;        // Reset command.
    parameter    [3:0]        Read        = 3;        // Read command.
    parameter    [3:0]        Write        = 4;        // Write command.
    parameter    [3:0]        Register    = 5;        // Status register checking command.
    parameter   [3:0]        Erase        = 6;        // Erase command.
    parameter   [3:0]        Idle        = 7;     // Reserve state..
    parameter   [3:0]        AutoSel        = 8;     // Auto Select command..
    
//-------------------------------------------------------------------------------
// PARAMETER DECLARATIONS FOR "OPERATIONS" USED IN THE ONE-HOT ENCODED FSM...
//-------------------------------------------------------------------------------
    parameter    [2:0]        op_rd_rst    = 1;    // Read/Reset command.
    parameter    [2:0]        op_write    = 2;    // Write command.
    parameter    [2:0]        op_erase    = 3;    // Erase command.
    parameter   [2:0]        op_reg        = 4;   // Status register.
    parameter   [2:0]        op_AutoSel    = 5;   // Auto select command.
    

//-------------------------------------------------------------------------------
// INTERNAL SIGNALS
//-------------------------------------------------------------------------------
    reg            [9:0]        state;            // Present state.
    reg            [9:0]        next;             // Next state.
    reg            [3:0]        command;          // Flash Command.
    reg            [2:0]        operation;        // Current Flash Operation.
    reg            [8:0]        delay_cnt;        // Counter for delays' calculation.
    reg            [8:0]        reg_cnt;          // Counter for Programming time.. (10 us).
    reg            [4:0]        rd2rd_cnt;        // Counter for successive bus reads..
    reg                        RP_done;          // Signal to indicate "RP trig to High" transition..
    reg         [15:0]        bus_data;         // Data to be thrown onto the DQ..
    reg         [2:0]        iteration;        // Counter to indicate the number of write cycles required for an operation.
    reg                        bus_en = 0;       // Tri state enable logic
    reg                        tri_en;           // Tri-state buffer -> enable signal
    reg         [2:0]        bus_cnt;
    reg                        W_halt;
    reg                        Reg_chk;          // Flag set to issue status register check command.
    reg                        REG_valid;        // Status register valid on bus
    reg                        ready;
    reg                        trig;
    reg                        err_flag;
    reg                        id_flag;
    reg                        rd_intrpt;
    reg                        FLASH_busy;       // Program operation in progress.
    reg                        SUCCESS;          // Program operation successful.
    reg                        FAIL;             // Program operation failed.


/* DESCRIPTION :
                This block ensures that any "state transitions" only take place
                on an active clock edge.. Reset used here is an asynchronous reset!
                state[IDLE] <= 1 means the present state of "IDLE" is true(boolean).
*/

always@(posedge CLK40MHz, posedge RST)
begin
    if(RST)
    begin
        state       <= 10'b0;                       
        state[IDLE] <= 1'b1;                  // Upon reset present state -> IDLE.
    end
    
    else
    state <= next;                            // State transitions take place on active clock edge (positive).
end


//-------------------------------------------------------------------------------
// Next State determining logic..
//-------------------------------------------------------------------------------

/* DESCRIPTION :
                This block is the "next state" decoding logic in the 1-hot encoded FSM.
                     whensoever the control enters a particular state, based on the stimulus
                     in the always block's senstitivity list the next state to which the
                     control should go is assigned.
*/

always@(init_done, WR_EN, RD_EN, FL_ERASE, ID_RD, FAIL, SUCCESS, command, state, delay_cnt, id_flag, W_halt, Reg_chk, rd_intrpt, operation, ready, rd2rd_cnt, iteration, trig)
begin
    next = 10'b0;

            case(1'b1)



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Instructor
Instructor
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Registered: ‎08-14-2007

Re: How do i invoke a verilog module from vhdl?

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It's probably not a good idea to have multiple parameters whose name only differs in

the case of the characters:

 

parameter [9:0] . . .

                    ERASE    = 5,        // STATE for 'FLASH ERASE' operation (block/chip).

 

and

 

parameter   [3:0]        Erase        = 6;        // Erase command.

 

VHDL, unlike Verilog, is not case sensitive, so it's not clear to me if you will

actually affect the correct parameter when you apply a generic to "Erase"

vs. "ERASE".

 

It's also not clear to me why you would want to change these parameters for a

particular instance of your code, as they just appear to be state encodings.

 

In any case, the parameter ERASE is a 10-bit vector and Erase is a 4 bit vector.

I would imagine these would translate into st_logic_vector(9 downto 0) and

std_logic_vector(3 downto 0) respectively.

 

HTH,

Gabor

-- Gabor
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Visitor nirmalapss
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Registered: ‎05-21-2012

Re: How do i invoke a verilog module from vhdl?

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hi,

Actually this code is developed by some else.....i am calling this verilog file in vhdl project ...as i dont have time to rewrite the entire logic in vhdl i have to call that function what i should do....

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Instructor
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Re: How do i invoke a verilog module from vhdl?

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What you should do depends on what you need from the Verilog module.

 

Do you really need to change the values of parameters in this module?  If not,

just get rid of the generics.

 

If you need to modify the parameter values, then I would suggest using a Verilog

wrapper to set the parameter values (assuming you can't get the generics working

from VHDL) and then instantiate the wrapper in VHDL.

 

Alternately, if you only need one instance of this Verilog module, you can edit the

Verilog code to set the default value of the parameters to the values you need.

 

- Gabor

-- Gabor
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Teacher rcingham
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Re: How do i invoke a verilog module from vhdl?

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"It's probably not a good idea to have multiple parameters whose name only differs in the case of the characters."

Wrong. It is definitely a very bad thing in any context involving VHDL.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Visitor nirmalapss
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Re: How do i invoke a verilog module from vhdl?

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I have chase the duplicated name like Erase,autosel ,now iam able the synthesize the code...thanx for identifying the problem...

 

 

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Teacher rcingham
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Re: How do i invoke a verilog module from vhdl?

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Excellent.
Can you mark the thread as solved?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Instructor
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Re: How do i invoke a verilog module from vhdl?

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@rcingham wrote:
Excellent.
Can you mark the thread as solved?

My thoughts as well.  However the original poster is the only one who can do that...

 

-- Gabor

-- Gabor
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