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jlarin
Adventurer
Adventurer
666 Views
Registered: ‎06-07-2012

How to do Post-Synthesis or Post-Implementation functionnal or timing simulation with a Zynq-7000

Hi,

I’ve been trying to refine our power estimation on the Zynq.  I first tried to run the Behavioral Simulation under Vivado 2019.1. to generate the .SAIF file but got limited results:

INFO: [Power 33-26] Design nets matched = 25 of 299201

0% of nets annotated

Looking at UG997 in more details, I figured out that to get good coverage from SAIF, you need to use the post_synthesis simulation results.  I ran the tutorial with success.  At step 7, page 31 there is an important note:

Note: The power reporting and analysis are not performed at the RTL level. They are performed at the gate level.

Furthermore, at lab2 section on page 38, the next step is to run the timing simulation on implemented design.

I just tried that with our design that runs fine Behavioral Simulation.  So going through the GUI, I launched the next simulation available:

 

The result is an error:

ERROR: [VRFC 10-2991] 'set_debug_level_info' is not declared under prefix 'inst' [c:/work/.../zynq_tb.sv:262]

It seems to me that the Zynq Vip is not supported in Post-Synthesis or Post-Implementation.

 

We can do the same test with the example design from Vivado.  I do Open Example Projet |Base Zynq |ZC706.  Let’s try Behavioral Simulation | run –all:

[2250] : M_AXI_GP0 : *ZYNQ_VIP_INFO : Done AXI Read for Starting Address(0x40000000) with Response 'OKAY'

2250 ns, running the testbench, data read from BRAM was 32'hdeadbeef

AXI VIP Test PASSED

Simulation completed

 

Then I ran the synthesis to enable the next simulation step. Then I launched Post-synthesis Functional Simulation. Here are the results:

Starting static elaboration

ERROR: [VRFC 10-2991] 'fpga_soft_reset' is not declared under prefix 'inst' [C:/work/basezynq/basezynq.srcs/sim_1/imports/base_zynq/zynq_tb.v:86]

...

ERROR: [VRFC 10-2991] 'read_data' is not declared under prefix 'inst' [C:/work/basezynq/basezynq.srcs/sim_1/imports/base_zynq/zynq_tb.v:94]

ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

 

Those signals not declared are the Zynq VIP functions (well, tasks actually…)

 

Beside the fact that Post-Synthesis or Post-Implementation simulation are neede to generate SAIF file, this looks to me like a huge usability hole for Zynq Parts: we can't simulate after the RTL Behavioral simulation!

Thank your for any pointers on how to fix that,

 

jf

 

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demarco
Xilinx Employee
Xilinx Employee
591 Views
Registered: ‎10-04-2016

Hi @jlarin ,

As you have discovered, the AXI VIP and IPs that use it synthesize to wires. This means they are not available to provide stimulus in Post-Synthesis or Post-Implementation simulation. The Zynq-7000 VIP and MPSoC VIP use AXI VIP and are subject to this limitation.

Given this, a SAIF file cannot be generated. For power analysis, a Vectorless Estimation method must be used. Please see UG907 for detail.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug907-vivado-power-analysis-optimization.pdf

Regards,

Deanna

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