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Contributor
Contributor
472 Views
Registered: ‎06-07-2012

How to fix file reference to trace through VIP model

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Hi,

 

I am simulating with Vivavo behaviorial simulator 2018.2.  I have a Zynq-7000 in my system and I am using the Zynq VIP. I want to trace into the Zynq VIP code.  I am trying to use the read_mem() method (system verilog function if you prefer) and it does not work as expect. When I try to step into the read_mem() to figure out what's wrong, I can step into the code, but I cannot see the source or any local data:

 

Stopped at time : 165410 ns : File "C:/work/iris3/gaia/testbench/zynq_tb.v" Line 171
run: Time (s): cpu = 00:00:20 ; elapsed = 00:02:04 . Memory (MB): peak = 1831.133 ; gain = 0.000
step
Stopped at time : 165410 ns : File "/proj/xbuilds/2018.2_0614_1954/infra/XSIM/lin/.cxl.ip/incl/processing_system7_vip_v1_0_5_apis.v" Line 300
WARNING: [Simulator 45-29] Cannot open source file /proj/xbuilds/2018.2_0614_1954/infra/XSIM/lin/.cxl.ip/incl/processing_system7_vip_v1_0_5_apis.v: file does not exist.
step
Stopped at time : 165410 ns : File "/proj/xbuilds/2018.2_0614_1954/infra/XSIM/lin/.cxl.ip/incl/processing_system7_vip_v1_0_5_apis.v" Line 794
step
Stopped at time : 165410 ns : File "/proj/xbuilds/2018.2_0614_1954/infra/XSIM/lin/.cxl.ip/incl/processing_system7_vip_v1_0_5_apis.v" Line 796

   

This is pretty much like the situation described in https://forums.xilinx.com/t5/Simulation-and-Verification/XPM-FIFO-ASYNC-simulation-xpm-fifo-sv-file-does-not-exist/m-p/836739#M21268 , except that I WANT to see what's inside.    I mean, the code isn't encrypted, it is available in the project sub-directory:

    /* read_memory */       <---- line 292
    task automatic read_mem;
      input [addr_width-1:0] start_addr;
      input [max_burst_bytes_width :0] no_of_bytes;
      output[max_burst_bits-1 :0] data;
      reg [1:0] mem_type;
      integer succ;
      begin
        mem_type = decode_address(start_addr);     <-- line 300
        if(check_addr_aligned(start_addr)) begin    
          case(mem_type)
          OCM_MEM : begin
                  if (!C_HIGH_OCM_EN)
                    ocmc.ocm.read_mem(data,start_addr,no_of_bytes); 
                  else
                    ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); 
                    if(DEBUG_INFO)
                      $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO,  start_addr, no_of_bytes); 
                    end 

It would seem that the simulator uses some pre-compiles files from a Linux directory instead of the generated model file from my hard-drive.  Is that any trick to change that behavior?

 

Thanks,

 

jf

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Contributor
Contributor
276 Views
Registered: ‎06-07-2012

Re: How to fix file reference to trace through VIP model

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The solution to the problem is to disable the use of the pre-compiled libraries in the project setting:

pcl.JPG

 

Then you can trace into Library code.

 

jf

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3 Replies
Moderator
Moderator
440 Views
Registered: ‎04-24-2013

Re: How to fix file reference to trace through VIP model

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Hi @jlarin,

 

To the best of my knowledge there is no trick that allows you to change the default behaviour.

 

What you could try is to use the export_simulation tcl command to create a script that runs the simulation.

Within the script you could change the files used to the RTL that you want to use as opposed to the pre comiled version.

 

Best Reagrds
Aidan

 

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Contributor
Contributor
416 Views
Registered: ‎06-07-2012

Re: How to fix file reference to trace through VIP model

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Hi @amaccre,

 

I tried to add the files to the project in the simulation fileset, but Vivado does not see those file as used by the simulation so they are not included in the compilation script.

 

I generated the script and tried to add the files manually, but I then get a compilation problem with the .SV file:

ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mod
e [c:/work/iris3/gaia/backend/Gaia_ZC706_test.srcs/sources_1/bd/gaia_zynq/ipshar
ed/70fd/hdl/processing_system7_vip_v1_0_5_apis.v:11]

 

I think we are getting too far from the objective here.  The goal is to debug why the IP simulation model does not behave as expected.  At the same time, the tools allows us to trace in the code with the Step command, still does not display the source code or enable the user to see the local variables and data structure.  I would call this a "severe limitation" at least, if not a "utilisation problem"  Is there any way to forward that as an improvement request to the design team?

 

Best Regards,

 

jf

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Contributor
Contributor
277 Views
Registered: ‎06-07-2012

Re: How to fix file reference to trace through VIP model

Jump to solution

The solution to the problem is to disable the use of the pre-compiled libraries in the project setting:

pcl.JPG

 

Then you can trace into Library code.

 

jf

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