How to simulate the PLL & BUFG primitives?

[ldm.eth]

Hi All,

How can I simulate the design, which includes the PLL (Advanced Phase Locked Loop PLL2_ADV primitive)? 

Where can I find a simulation model of the PLL2_ADV? How could I bypass the PLL locking phase? 

How can I simulate BUFG, which is also a part of my design?

Thank you!

[dpaul24]

@ldm.eth,

For VHDL, I guess the following libraries take care of the Xilinx primitives, providing a simulation model.-

library unisim;
use unisim.vcomponents.all;

How can I simulate BUFG, which is also a part of my design?

You just instiantiate a BUFG in your design, call the unisim library, and drive the relevant signals from your testbench for simulation.

[ldm.eth · Accepted solution]

And what about Verilog? What should I do?

[dpaul24]

Google or search Xilinx forum!

I have given you the hint, good enough for you to pick up the rest...now don't be lazy! :-p

[ldm.eth]

Sure, thanks :-) Marking your answer as a solution .... :-)

[shantzis62]

Hi all,
I'm wondering if you could state what the answer is for Verilog. It isn't a question of laziness. It's that I'm very new at this and trying to figure out this exact question: How to simulate PLL2.

Thanks so much in advance!

[shantzis62]

Nevermind, all. Apparently, it just simulates a PLL primitive when you instantiate it. I just had it wired incorrectly..