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Newbie mvsonu2
Newbie
262 Views
Registered: ‎03-04-2019

I am gettin X's in my simmulation

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_unsigned.ALL;
--se IEEE.STD_LOGIC_arith.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
Port ( a1 : in STD_LOGIC_VECTOR (31 downto 0);
b1 : in STD_LOGIC_VECTOR (31 downto 0);
c1 : in STD_LOGIC_VECTOR (4 downto 0);
r : out STD_LOGIC_VECTOR (31 downto 0);
e1 : out STD_LOGIC);
end ALU;

architecture Behavioral of ALU is
signal sum1: std_logic_vector (31 downto 0);
signal c: std_logic_vector (32 downto 0);
signal carry_i: std_logic := '0';
signal carry_o: std_logic;
signal sum_result: std_logic_vector (31 downto 0);
signal sum_sub: std_logic_vector (31 downto 0);
signal sum_and: std_logic_vector (31 downto 0);
signal sum_or: std_logic_vector (31 downto 0);
signal sum_nor: std_logic_vector (31 downto 0);
signal temp1: std_logic_vector (31 downto 0);
signal temp2: std_logic_vector (31 downto 0);
signal d: std_logic := '1';
signal e: std_logic := '0';
--signal ans: std_logic_vector (31 downto 0);

 

component full32_adder

Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
b : in STD_LOGIC_VECTOR (31 downto 0);
carry_in : in STD_LOGIC:='0';
sum : out STD_LOGIC_VECTOR (31 downto 0);
carry_out : out STD_LOGIC);


end component;

component bit32_inverter
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
z : out STD_LOGIC_VECTOR (31 downto 0));

end component;

begin
--for addition
FB0: full32_adder port map (a1, b1, carry_i, sum1, carry_o);
sum_result <= sum1;

--for subtract
FB1: bit32_inverter port map (b1, temp1);
temp2 <= temp1;
FB2: full32_adder port map (a1, temp2, carry_i, sum1, carry_o);
sum_sub <= sum1;

--for and
sum_and <= a1 and b1;

--for or
sum_or <= a1 or b1;
--for nor
sum_nor <= a1 nor b1;

with c1 select
r <= sum_result when "00010",
sum_sub when "00110",
sum_or when "00001",
sum_and when "00000",
sum_nor when "01100",
"00000000000000000000000000000000" when others;
--e <= d when ans = x"00000000";
--e <= e1;


end Behavioral;

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1 Reply
Scholar richardhead
Scholar
230 Views
Registered: ‎08-01-2012

Re: I am gettin X's in my simmulation

Xs occur when you drive the same signal from multiple sources.

In your case, sum1 and  carry_o are driven from two different full32_adder components.

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