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jhgf
Contributor
Contributor
1,236 Views
Registered: ‎09-24-2016

ILA clock above 400 MHZ with ZynQ7 FPGA

Hi, 

 

I'm using Zynq7 (xc7z010-clg400-3) FPGA.

I have a design with an ILA. The ILA clock is generated from an MMCM. With any clock generated from the MMCM and below 400MHZ, i see my signals in the hardware manager. With clocks above 400 MHZ, no signals appear in the hardware manager and there is an error saying that the clock must be free running.

 

Any explanation? i want to use a clock greater than 400 MHZ for my ILA.

 

Thank you

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thakurr
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1,190 Views
Registered: ‎09-15-2016

 Hi @jhgf

 

What is your JTAG frequency? Free running clock means clock which does not depends on reset or any other control signals. Does the clock coming out of MMCM bypasses any other primitive before it reaches the ILA core? Please make sure that there is no dependency on any control signal.

Your ILA frequency should be double or more than double to JTAG frequency.

https://www.xilinx.com/support/answers/57934.html

 

Regards

Rohit

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Regards
Rohit
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jhgf
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Registered: ‎09-24-2016

@thakurr

my JTAG freq is 1500000000 HZ.

The clock generated from my MMCM is not controled by anything (no reset) and is directly connected to debug-hub and ILA input pins. 

Below 400 MHZ everything works fine. when i switched to 600 MHZ i get this error :

 

WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].

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arpansur
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Registered: ‎07-01-2015

Hi @jhgf,

 

Is the timing met in 600MHz design?

Thanks,
Arpan
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