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Participant
Participant
6,580 Views
Registered: ‎02-10-2012

INIT_FILE for BRAM_TDP_MACRO

I have been using BRAM_TDP_MACRO for some time without problems, but as soon as I try to define an initialization file, everything goes wrong!

 

I use Modelsim SE 10, and I get this error message any time I invoke BRAM_TDP_MACRO with INIT_FILE having a value different than NONE:

 

# Loading unisim.vpkg(body)
# Loading unisim.rb18_internal_vhdl(rb18_internal_vhdl_v)#1
# ** Fatal: (vsim-3471) Slice range (1 to 2) does not belong to the prefix index range (1 to 1).
#    Time: 0 ps  Iteration: 0  Process: /sram_tb/BRAM_TDP_MACRO_inst/ramb_bl/ramb18_dp_bl/ram18_bl/TDP/RAMB18E1_TDP_inst/prcs_clk File: D:/Xilinx/ISE_DS/ISE/artix7/vhdl/src/unisims/primitive/RAMB18E1.vhd
# FATAL ERROR while loading design
# Error loading design

 

This is my instantiation code:

BRAM_TDP_MACRO_inst : BRAM_TDP_MACRO
generic map (
    BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
    DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
    DOA_REG => 0, -- Optional port A output register (0 or 1)
    DOB_REG => 0, -- Optional port B output register (0 or 1)
    INIT_A => X"000000000", -- Initial values on A output port
    INIT_B => X"000000000", -- Initial values on B output port
    INIT_FILE => "V7_DP_Block_Ram.mif",
    READ_WIDTH_A => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
    READ_WIDTH_B => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
    SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
    -- "GENERATE_X_ONLY" or "NONE"
    SRVAL_A => X"000000000", -- Set/Reset value for A port output
    SRVAL_B => X"000000000", -- Set/Reset value for B port output
    WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
    WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
    WRITE_WIDTH_A => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
    WRITE_WIDTH_B => 16 -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
    )
port map (
    DOA => tx_data_outA_ac1_i, -- Output port-A data, width defined by READ_WIDTH_A parameter
    DOB => tx_data_outB_ac1_i, -- Output port-B data, width defined by READ_WIDTH_B parameter
    ADDRA => tx_addrA(9 downto 0), -- Input port-A address, width defined by Port A depth
    ADDRB => tx_addrB(9 downto 0), -- Input port-B address, width defined by Port B depth
    CLKA => clk1, -- 1-bit input port-A clock
    CLKB => clk2, -- 1-bit input port-B clock
    DIA => tx_data_inA_ac1_i, -- Input port-A data, width defined by WRITE_WIDTH_A parameter
    DIB => tx_data_inB_ac1_i, -- Input port-B data, width defined by WRITE_WIDTH_B parameter
    ENA => tx_csA, -- 1-bit input port-A enable
    ENB => tx_csB, -- 1-bit input port-B enable
    REGCEA => '0', -- 1-bit input port-A output register enable
    REGCEB => '0', -- 1-bit input port-B output register enable
    RSTA => '0', -- 1-bit input port-A reset
    RSTB => '0', -- 1-bit input port-B reset
    WEA => int_weA, -- Input port-A write enable, width defined by Port A depth
    WEB => int_weA -- Input port-B write enable, width defined by Port B depth
);

 

What can the problem be?

 

Thanks,

 

Michele

 

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5 Replies
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Xilinx Employee
Xilinx Employee
6,576 Views
Registered: ‎07-16-2008

Hi Michele,

 

What ISE version are you using?

Can you attach the testcase?

 

 

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Participant
Participant
6,573 Views
Registered: ‎02-10-2012

I am using ISE 13.4, downloaded from the website a few weeks ago, and I compiled the simulation libraries on my machine with compxlib for all FPGA targets.

 

Unofrtunately I cannot attach the main testcase, but in any case I have this problem every time I try to add an "init file": this is the mini-testbench I use just for the different RAM wrappings: it give me the error as soon as I put a file instead of "NONE". 

 

BTW the macro does not seem to be too stable: if I wrap it more than once (I need it for portability) Modelsim hungs up when loading the design...

 

Thanks!

 

Michele

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Xilinx Employee
Xilinx Employee
6,563 Views
Registered: ‎07-16-2008

I made a simple testcase here and can reproduce the issue with regards to INIT_FILE.

It looks an issue in the VHDL unisims model of RAMB18E1. If using verilog model, there's no such error.

 

Please open a webcase with Xilinx Technical Support for investigation.

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Explorer
Explorer
6,465 Views
Registered: ‎06-17-2012

What is the format of your NIT_FILE?

 

When you use the INIT_FILE, is there any '.bmm' file generated in your project?

 

I am also trying to initialize RAM like this, but come up different trouble.

 

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Visitor
Visitor
690 Views
Registered: ‎04-23-2015

I am having unexpected problems with a BRAM_TDP_MACRO. The instantiates follows.

I believe port-A works, but port-B always outputs zero.

Should be trivial; any ideas ?

generate for (ii = 0; ii < HRAM_PAGES; ii = ii + 1)                 //generate block memories (HAM_PAGES==64)
   begin:mem                                                        //
   assign blockEn[ii] = (ii == m2h_i.pAdr);                         //physical adr part
   assign hostEn[ii]  = (ii == hostRdAdr[14:9]);                    //       "
      BRAM_TDP_MACRO                                                //
        #(.BRAM_SIZE("18Kb"), .DEVICE("7SERIES"),
           .WRITE_WIDTH_A(36), .READ_WIDTH_A(36), .WRITE_WIDTH_B(36), .READ_WIDTH_B(36),
          .DOA_REG(1), .DOB_REG(1), .WRITE_MODE_A("READ_FIRST"),.WRITE_MODE_B("READ_FIRST"))
       memory(.RSTA(rst_i), .REGCEA(1), .CLKA(clk),
                  .ENA(blockEn[ii]), .WEA(blockEn[ii] & wrEn),
                  .ADDRA(hramAdrInBlok), .DOA(rowBufOut[ii]), .DIA(s2hData_i[31:0]),
              .RSTB(rst_i), .REGCEB(1), .CLKB(clk),
                  .ENB(hostEn[ii]),  .WEB(0),
                  .ADDRB(hostRdAdr[8:0]), .DOB(hostBufOut[ii]),.DIB(32'h0)
             );
   end //generate...

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