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Adventurer
Adventurer
6,588 Views
Registered: ‎12-21-2011

ISIM command line tutorial

Hi guys

 

As my project grows, navigating it by mouse is getting more and more complicating and frustrating.

 

One obvious solution to this problem is to launch my simulation in ISIM from the command line, so that all the parameters are always the and i don't have to set simulation time, wcfg file etc every time.

 

I thought that maybe we can compile here something like tutorial or manual, so that new users can refer to it without wasting time on how to do it.

 

Another thing is i didn't manage to launch simulation of my top level entity from command line, so i would also appreciate your help.

 

Here are some usefull sources of information that i found :

 

Plase feel free to let me know if you found anything usefull for command line simulation using ISim

 

NOTE: i'm using Windows XP to make all actions listed below

 

This is what i know i need to do to launch isim from command line:

 

  1. write/generate a *.prj file, which list all files that need to be compiled, together with the proper compile order. It's not that trivial. You can get hald-finished prj file of your design from top level directory of Xilinx ISE project. However it will not contain all files necessary to compile them. This is how this raw file generated by ISE looks like in my case:

 

vhdl isim_temp "ipcore_dir/m_multiplier16bit/m_multiplier16bit.vhd"
vhdl isim_temp "packages/p_global_conf.vhd"
vhdl isim_temp "source/m_ser2par.vhd"
vhdl isim_temp "packages/p_shifting_register.vhd"
vhdl isim_temp "packages/p_image_data_rx_types.vhd"
vhdl isim_temp "packages/p_data_standarizer_types.vhd"
vhdl isim_temp "source/m_image_data_rx.vhd"
vhdl isim_temp "source/m_flag_ack.vhd"
vhdl isim_temp "source/m_bram_read_cntrl.vhd"
vhdl isim_temp "source/m_address_computer.vhd"
vhdl isim_temp "source/m_2channel_fifo.vhd"
vhdl isim_temp "packages/p_imagepkg.vhd"
vhdl isim_temp "source/m_shifting_register.vhd"
vhdl isim_temp "source/m_mcb_write_controller.vhd"
vhdl isim_temp "source/m_mcb_read_controller.vhd"
vhdl isim_temp "source/m_data_standarizer.vhd"
vhdl isim_temp "source/m_image_sensor_model.vhd"
vhdl isim_temp "source/m_data_buffer.vhd"
vhdl isim_temp "testbench/tb_data_buffer.vhd"
verilog isim_temp "C:/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v"

 

This file contain all files visible in the ISE project navigatior, all source files, packages and top testbench file + verilog global file

 

Unfortunately this list is not full, i've got for example 3 IP cores generated using Xilinx ISim:

 

 

  • MCB block - Memory Controller Block - it's a SDRAM controller core (UG388.pdf)
  • Multiplier - hardware multiplier 
  • Block RAM - Block Memory Generator (DS512.pdf)

I tried to add those files, and this is how it look right now:

 

vhdl  		work  "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/iodrp_controller.vhd"
vhdl  		work  "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/iodrp_mcb_controller.vhd"
vhdl  		work  "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/m_mcb_ddr3.vhd"
vhdl  		work  "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/mcb_raw_wrapper.vhd"
vhdl 	 	work  "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/mcb_soft_calibration.vhd"
vhdl  		work  "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/mcb_soft_calibration_top.vhd"
vhdl  		work  "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/memc1_infrastructure.vhd"
vhdl  		work  "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/memc1_wrapper.vhd"

vhdl  		work  "../ipcore_dir/m_bram_pixel_memory/m_bram_pixel_memory.vhd"

vhdl 		work  "../ipcore_dir/m_multiplier16bit/m_multiplier16bit.vhd"

vhdl 		work  "../packages/p_global_conf.vhd"
vhdl 		work  "../source/m_ser2par.vhd"
vhdl 		work  "../packages/p_shifting_register.vhd"
vhdl 		work  "../packages/p_image_data_rx_types.vhd"
vhdl 		work  "../packages/p_data_standarizer_types.vhd"
vhdl 		work  "../source/m_image_data_rx.vhd"
vhdl 		work  "../source/m_flag_ack.vhd"
vhdl 		work  "../source/m_bram_read_cntrl.vhd"
vhdl 		work  "../source/m_address_computer.vhd"
vhdl 		work  "../source/m_2channel_fifo.vhd"
vhdl 		work  "../packages/p_imagepkg.vhd"
vhdl 		work  "../source/m_shifting_register.vhd"
vhdl 		work  "../source/m_mcb_write_controller.vhd"
vhdl 		work  "../source/m_mcb_read_controller.vhd"
vhdl 		work  "../source/m_data_standarizer.vhd"
vhdl 		work  "../source/m_image_sensor_model.vhd"
vhdl 		work  "../source/m_data_buffer.vhd"
vhdl 		work  "../testbench/tb_data_buffer.vhd"

verilog 	work  "C:/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v"

verilog  	work  ../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/sim/ddr3_model_c1.v -d x2Gb -d sg15E -d x16 -i ./

 

My *prj files was copied to /scripts directory, hence "../" in all paths

 

2. Second step is to write *bat file that launches fuse compiler with all needed parameters and then, if compilation succeeds, launches ouput exe file .

 

This is how my file looks like:

 

echo Simulation Tool: ISIM
fuse work.tb_data_buffer work.glbl -prj tb_data_buffer.prj -L unisim -L secureip -timeprecision_vhdl ps -o tb_data_buffer.exe -incremental
tb_data_buffer.exe -gui -tclbatch m_data_buffer.tcl -wdb tb_data_buffer.wdb -log isim_data_buffer.log -view ../waveform_confs/tb_data_buffer.wcfg
echo done

 

 fuse is the Xilinx compiler, parameters are:

  • work.tb_data_buffer  - top level testbench file with wht library name at the begining (note that the same library name as in the prj file)
  • work.glbl - verilog global file
  • -prf tb_data_buffer.prf - *.prj file from the previous step
  • -L unisim, -L secureip - additional linked libraries 
  • -timeprecision_vhdl ps - VHDL - only parameter 
  • -o tb_data_buffer.exe - output file
  • -incremental - don't compile already compiled files

second line is the output executable that should be launched with -gui option. This is what actually launches ISim, it's parameters are :

 

  • -gui - launches ISim 
  • -tclbatch m_data_buffer.tcl - Tcl script - see next step
  • -wdb tb_data_buffer.wdb - waveform data base file that stores all simulation data
  • -log isim_data_buffer.log - log file for ISim, stores all console from ISim - very usefull
  • -view - custom waveform configuration file

 

3. This is how my Tcl file looks like: 

 

onerror {resume}

isim set radix unsigned

run 600 us

quit

 

It's way if scripting ISim to do things like set simulation time, set radixes, add waves and many others.

 

From what i learned , those 3 files should be enough to successfully simulate your design from command line. Note that you should launch your *.bat file from ISE Design Suite Command Prompt, which is available in the Start menu.

 

 

 

Needed files:

  1. *prj that list all source files
  2. *bat / *sh script to launch fuse and isim/modelsim
  3. *tcl script to configure isim/modelsim 

 

And this is my problem:

 

It's hard to correctly include all files to you *prj file, for example in my case after succesfully including all MCB-related file, i've got errors that not all files related to my Block Memory Core are included, and fuse failed

 

C:\Documents and Settings\mapedd\Pulpit\GIT\K40_TOP\scripts>fuse work.tb_data_buffer work.glbl -prj tb_data_buffer.prj -L unisim -L secureip -timeprec
ision_vhdl ps -o tb_data_buffer.exe -incremental
Running: C:\Xilinx\13.3\ISE_DS\ISE\bin\nt\unwrapped\fuse.exe work.tb_data_buffer work.glbl -prj tb_data_buffer.prj -L unisim -L secureip -timeprecisio
n_vhdl ps -o tb_data_buffer.exe -incremental
ISim O.76xd (signature 0x2f00eba5)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Analyzing Verilog file "C:/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work
Analyzing Verilog file "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/sim/ddr3_model_c1.v" into library work
Parsing VHDL file "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/iodrp_controller.vhd" into library work
Parsing VHDL file "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/iodrp_mcb_controller.vhd" into library work
Parsing VHDL file "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/m_mcb_ddr3.vhd" into library work
Parsing VHDL file "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/mcb_raw_wrapper.vhd" into library work
Parsing VHDL file "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/mcb_soft_calibration.vhd" into library work
Parsing VHDL file "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/mcb_soft_calibration_top.vhd" into library work
Parsing VHDL file "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/memc1_infrastructure.vhd" into library work
Parsing VHDL file "../ipcore_dir/m_mcb_ddr3/m_mcb_ddr3/user_design/rtl/memc1_wrapper.vhd" into library work
Parsing VHDL file "../ipcore_dir/m_bram_pixel_memory/m_bram_pixel_memory.vhd" into library work
ERROR:HDLCompiler:104 - "../ipcore_dir/m_bram_pixel_memory/m_bram_pixel_memory.vhd" Line 70: Cannot find <blk_mem_gen_v6_3> in library <xilinxcorelib>
. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
ERROR:HDLCompiler:854 - "../ipcore_dir/m_bram_pixel_memory/m_bram_pixel_memory.vhd" Line 55: Unit <m_bram_pixel_memory_a> ignored due to previous erro
rs.
VHDL file ../ipcore_dir/m_bram_pixel_memory/m_bram_pixel_memory.vhd ignored due to errors

 

 Look that Block Memory module have some missing submodule, does anybody know how to fix this? I'm attaching my ipcore_dir as a reference

 

ERROR:HDLCompiler:104 - "../ipcore_dir/m_bram_pixel_memory/m_bram_pixel_memory.vhd" Line 70: Cannot find <blk_mem_gen_v6_3> in library <xilinxcorelib>

Another question : 

 

Is there an option in ISE to automatically generate valid prj file?

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