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Newbie
Newbie
520 Views
Registered: ‎10-16-2020

ISIM simulation won't work with simple shift registers

Hi,

 

I am working with ISE 14.7 with its ISIM simulator. I am programming some excercises from a book. The topic is about shift registers.

My problem is that I can't get any output out of the simulation. I would say that my program is correct. I also tried the soloution from the book and that also won't work.

Do you have an idea?

 

Best regards

library ieee;
use ieee.std_logic_1164.all;

entity example_6 is
    port(
        init : in  std_logic;
        clk  : in  std_logic;
        q    : out std_logic;
    );
end entity;

architecture behaviour of example_6 is
    signal shift_1, shift_2, shift_3 : std_logic_vector(3 downto 0);
    signal mux_q                     : std_logic;

begin

    ---------------------
    -- initialisation

    init_d : process(clk)
    begin
        if (init = '1' and rising_edge(clk)) then
            shift_1 <= "1010";
            shift_2 <= "0101";
        end if;
    end process init_d;

    ---------------------
    -- shift register 1

    shift1 : process(clk)
    begin
        if rising_edge(clk) then
            shift_1 <= shift_1(0) & shift_1(3 downto 1);
        end if;
    end process shift1;

    ---------------------
    -- shift register 2

    shift1 : process(clk)
    begin
        if rising_edge(clk) then
            shift_2 <= shift_2(0) & shift_2(3 downto 1);
        end if;
    end process shift2;

    ---------------------
    -- shift register 3

    shif_3 <= shift_2;

    ---------------------
    -- 2x1 MUX

    mux_q <= shift_1(0) when shift_3(0) = '0' else shift_2(0);

    ---------------------
    -- output

    q <= mux_q;

end architecture;

    

 

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12 Replies
Highlighted
Newbie
Newbie
506 Views
Registered: ‎10-16-2020

Sorry that I can't show you the circuit or the output of the simulation. This is due to my environment on my pc.
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Scholar
Scholar
499 Views
Registered: ‎08-07-2014

@Sarg_Nagel ,

Can you please post the screenshot of the simulation Window?

Also please post the testbench code.

 

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Newbie
Newbie
491 Views
Registered: ‎10-16-2020

Here is my testbench::

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY testbench IS
END testbench;
 
ARCHITECTURE behavior OF testbench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT example_6
    PORT(
         init : IN  std_logic;
         clk : IN  std_logic;
         q : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal init : std_logic := '0';
   signal clk : std_logic := '0';

 	--Outputs
   signal q : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: example_6 PORT MAP (
          init => init,
          clk => clk,
          q => q
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
		
		init <= '1';
		wait for 20 ns;
		init <= '0';

      wait;
   end process;

END;
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Highlighted
Newbie
Newbie
489 Views
Registered: ‎10-16-2020

Here is my simulation:
Unbenannt.png

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Highlighted
476 Views
Registered: ‎06-21-2017

There is  a typographical error in your code.

    ---------------------
    -- shift register 3

    shif_3 <= shift_2;

    ---------------------

shif_3 should be shift_3.  To help debug problems in the future, you can add signals inside the component you are testing to the waveform plot. 

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Scholar
Scholar
474 Views
Registered: ‎08-07-2014

@Sarg_Nagel ,

 In the waveform window, put the internal signals so that you can follow the bits change.

Do you also have a successful compilation?

--- update---

@bruce_karaffa ,

shif_3 should be shift_3.

xsim compiler should complain in that case and @Sarg_Nagel should pay attention too that!

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Newbie
Newbie
471 Views
Registered: ‎10-16-2020

Thanks but that came through the copying process. In original it's correct.
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Newbie
Newbie
467 Views
Registered: ‎10-16-2020

Thanks, I will do this.
(I tested if one shift register if it works, but I got also no output.)
Yes, the compilation was successful with ISIM and also GHDL.
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Scholar
Scholar
465 Views
Registered: ‎08-07-2014

@Sarg_Nagel ,

Thanks but that came through the copying process. In original it's correct.

I do not understand, if you are copy pasting the entire code from the original location how can there be a typo here? Copy pasting line by line from the original location would be stupid to do. Nevertheless...

Try simulating after replacing this...

 

   init_d : process(clk)
    begin
        if rising_edge(clk) then
            if init = '1' then
                shift_1 <= "1010";
                shift_2 <= "0101";
            end if;
        end if;
    end process init_d;

 

 

Also since you do not have a reset, initialize the registers like - signal shift_1, shift_2, shift_3 : std_logic_vector(3 downto 0) := "0000";

 

To me it looks like the fill values are being missed because init = '1' edge is for some reason being missed. Can't say for sure though.

 

 

Next time please show all the internal signals i n the wave-from window screenshot.

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Newbie
Newbie
440 Views
Registered: ‎10-16-2020

I do not understand, if you are copy pasting the entire code from the original location how can there be a typo here? Copy pasting line by line from the original location would be stupid to do. Nevertheless...

Because of my environment at work I had to copy the code by hand, I couldn't just copy paste it. That's why the typo is not in the original but in the copied one.

Next time please show all the internal signals i n the wave-from window screenshot.

Thank you. I will do it on monday and will show you the simulation result.

 

 

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Teacher
Teacher
438 Views
Registered: ‎07-09-2009

A few VHDL things.

Don't code like this

(init = '1' and rising_edge(clk))

code explicitly,
this assuming you want an asynchronous init

if init = '1' then
{ code }
elsif rising_edge( clk ) then
{code}
else
{ code }
endif;



second I dont know if it make any difference, but looking at my old code, I always seem to shift the other way .

shift_a <= shift_1( shift-1'left -1 downto 0 ) & shift_1( shift_1'left );

Also, remember that SRL's don't all have reset / enables , cant' remember what chips have what,
but look at the code, and check if you want it to go into a SRL.


And just a head sup,
you don't need the component definition in the test bench,


regarding the test bench
your only showing the top level signals,

drill down into the design, and see what the shift registers have on them might be informative.






<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Highlighted
Scholar
Scholar
428 Views
Registered: ‎08-07-2014

@drjohnsmith ,

I did not want to confuse the OP with what needs to be done if a reset is involved or why is it important to have a reset. I also ignored the cause the the init might be a replacement for reset (again discussing whether it is async or sync would likely confuse the OP I guess).

Just wanted to help him get a simple piece of code and its TB running with the desired simulation outputs.

However if the OP wants, a discussion can started if the init is to behave as a reset and how should the RTL look like for sync or async cases.

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