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Visitor
Visitor
7,456 Views
Registered: ‎09-27-2014

ISim: from console command to verilog

Hi, i'm trying to write a verilog test-bench file for my design. I need to force the values of two registers. I can do it from the command line with this: # isim force add {/full_system_tb/uut/interface/led_reg_1} 010 -radix bin

 

But i want to do this from my verilog test bench, What's the syntax to do this?

 

Thanks!

 

 

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Xilinx Employee
Xilinx Employee
7,448 Views
Registered: ‎10-24-2013

Re: ISim: from console command to verilog

Hi,
Instantiate your uut in the testbench and assign value to led_reg_1
sample testbench @ http://www.testbench.in/TB_08_CLOCK_GENERATOR.html
Thanks,Vijay
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Professor
Professor
7,418 Views
Registered: ‎08-14-2007

Re: ISim: from console command to verilog

Assuming your test bench is full_system_tb as shown in the hierarchy you posted, you can force variables (reg) in lower level modules using a period (.) as the hierarchy separator.  In Verilog a procedural "force" can be used in a block (always or initial) and when you want you can also use "release" to allow the signal to be driven by its original source.  So for example:

 

initial begin

  #100 force uut.interface.led_reg_1 = 3'b010;

  #1000 release uut.interface.led_reg_1;

end

-- Gabor
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