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Newbie meldm
Newbie
781 Views
Registered: ‎03-11-2018

In simulation getting U as output

Hello,

I'm new to xilinx. I have 2 outputs and In my simulation I get 'U' for one of them. Please help me to solve this. Here is my code: 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bitSliceCode is
   Port ( M : in STD_LOGIC;
        S0 : in STD_LOGIC;  
        S1 : in STD_LOGIC;
        A : in STD_LOGIC;
        B : in STD_LOGIC;
        Cin : in STD_LOGIC;
        F : out STD_LOGIC;
        Cout : out STD_LOGIC);
end bitSliceCode;

architecture Behavioral of bitSliceCode is


begin
Mux: process(M) is
    begin
        if ( M='0' and S1='0' and S0='0' ) then
                F <= A and B ;
       elsif ( M='0' and S1='0' and S0='1' ) then
                F <= A or B ;
       elsif ( M='0' and S1='1' and S0='0' ) then
                F <= A xor B ;
       elsif ( M='0' and S1='1' and S0='1' ) then
                F <= A xnor B ;
       else
                F <= '0';
               Cout <='1';
       end if;
end process;
end Behavioral;

 

 

 

and the sim code:

 

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bitSim IS
END bitSim;
ARCHITECTURE behavior OF bitSim IS

COMPONENT bitSliceCode
PORT(
M : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
F : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;


signal M : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';
signal A : std_logic := '0';
signal B : std_logic := '0';
signal Cin : std_logic := '0';


signal F : std_logic;
signal Cout : std_logic;


constant clock_period : time := 10 ns;

BEGIN


uut: bitSliceCode PORT MAP (
M => M,
S0 => S0,
S1 => S1,
A => A,
B => B,
Cin => Cin,
F => F,
Cout => Cout
);


stim_proc: process
begin

M <= '0'; S1 <='0'; S0 <='0'; A <='1'; B <='1';
wait for clock_period;
M <= '0'; S1 <='0'; S0 <='0'; A <='1'; B <='0';
wait for clock_period;
M <= '0'; S1 <='0'; S0 <='0'; A <='0'; B <='1';
wait for clock_period;
M <= '0'; S1 <='0'; S0 <='0'; A <='0'; B <='0';
wait for clock_period;

M <= '0'; S1 <='0'; S0 <='1'; A <='0'; B <='0';
wait for clock_period;
M <= '0'; S1 <='0'; S0 <='1'; A <='1'; B <='0';
wait for clock_period;
M <= '0'; S1 <='0'; S0 <='1'; A <='0'; B <='1';
wait for clock_period;
M <= '0'; S1 <='0'; S0 <='1'; A <='1'; B <='1';
wait for clock_period;

M <= '0'; S1 <='1'; S0 <='0'; A <='0'; B <='0';
wait for clock_period;
M <= '0'; S1 <='1'; S0 <='0'; A <='1'; B <='0';
wait for clock_period;
M <= '0'; S1 <='1'; S0 <='0'; A <='0'; B <='1';
wait for clock_period;
M <= '0'; S1 <='1'; S0 <='0'; A <='1'; B <='1';
wait for clock_period;

M <= '0'; S1 <='1'; S0 <='1'; A <='1'; B <='1';
wait for clock_period;
M <= '0'; S1 <='1'; S0 <='1'; A <='1'; B <='0';
wait for clock_period;
M <= '0'; S1 <='1'; S0 <='1'; A <='0'; B <='1';
wait for clock_period;
M <= '0'; S1 <='1'; S0 <='1'; A <='0'; B <='0';
wait for clock_period;

M <= '0';
wait for clock_period; 

wait;
end process;

END;

 

 

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3 Replies
Moderator
Moderator
768 Views
Registered: ‎05-31-2017

Re: In simulation getting U as output

Hi @meldm,

The output Cout is shown as U because you haven't covered the scenario in your test bench when the value for Cout gets assigned.

So, run simulation after using the below statements in your test bench so that it covers the condition for Cout to get assigned.

M <= '1';
wait for clock_period;

for_sim_tb.JPG

When M is 1 then the condition in the UUT executes and assigns the value to Cout.

 

Thanks & Regards,

A.Shameer

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Newbie meldm
Newbie
718 Views
Registered: ‎03-11-2018

Re: In simulation getting U as output

Thank you very much for help but I get U for output F. There isn't any problem with Cout. Do you have any idea why this could happen?

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Scholar richardhead
Scholar
708 Views
Registered: ‎08-01-2012

Re: In simulation getting U as output

Because you are missing signals from the sensitivity list in the mux process. Currently it is only sentitive to M, and M initialises to 0 and is '0' throughout, so there are no 'event on M, and nothing will be muxed.

 

You need to add S0, S1, A and B to the sensitivity list.

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