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Registered: ‎08-07-2018

Invalid reference 'u_g1_ipcat_xadc' in defparam; target resolves below VHDL scope 'u_g1_core_ctrl_status'.

Greetings ... I commented that a couple of days ago I have been doing simulation tests of a verilog project in Modelsim SE-64 10.5 from the compiled libraries of Vivado 2017.3, in which I have obtained the desired results. But now I need to convert this whole project to vhdl, so I started converting the module g1_core_ctrl_status to vhdl, and try the simulation, but I only get the error that is shown in the attached image. Can someone please help me with this problem?
I leave attached an image where I show the hierarchy of my current project, the file g1_core_ctrl_status.v, g1_ipcat_xadc.v and local_g1_test_bench.sv of simulation where the error is generated, in addition to a report Modelsim of the simulation test of the verilog project that worked correctly.

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Registered: ‎09-15-2016

Re: Invalid reference 'u_g1_ipcat_xadc' in defparam; target resolves below VHDL scope 'u_g1_core_ctrl_status'.

Hi @cesar182 ,

As from the shared files and the error message, looks like the issue occurs due to the below line of code in test bench:

defparm u_g1_top.u_g1_core_ctrl_status.u_g1_ipcat_xadc.inst.SIM_MONITOR_FILE = "C:/ProgramData/Teradyne/FPGA/VivadoProjects/RSBsdApp0x3020Revid_0x4/RsApp/RsApp.ip_user_files/mem_init_files/g1_xadc_sim_file.txt";

Can you please make sure that the hierarchical references are correct in the above line and can you please share the complete test case to reproduce this issue at our end and check. 

The supported Modelsim version with Vivado 2017.3 is Modelsim10.6b. Hence, please use supported version of modelsim to compile the simulation libraries and to run simulation in it.


Thanks & Regards,
Sravanthi B
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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