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Contributor
Contributor
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Registered: ‎08-07-2018

Invalid reference 'u_g1_ipcat_xadc' in defparam; target resolves below VHDL scope 'u_g1_core_ctrl_status'.

Greetings ... I commented that a couple of days ago I have been doing simulation tests of a verilog project in Modelsim SE-64 10.5 from the compiled libraries of Vivado 2017.3, in which I have obtained the desired results. But now I need to convert this whole project to vhdl, so I started converting the module g1_core_ctrl_status to vhdl, and try the simulation, but I only get the error that is shown in the attached image. Can someone please help me with this problem?
I leave attached an image where I show the hierarchy of my current project, the file g1_core_ctrl_status.v, g1_ipcat_xadc.v and local_g1_test_bench.sv of simulation where the error is generated, in addition to a report Modelsim of the simulation test of the verilog project that worked correctly.

modelsimError.PNG
myhierarchy.PNG
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