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inflector
Observer
Observer
1,950 Views
Registered: ‎08-29-2017

Misleading error message for extra comma at end of ports list for module instance

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If you have an extra comma at the end of the port list in a module instantiation, like this:

i2c_fifo fifo (
.srst(reset | clear),
.clk(clock),
.wr_en(fifo_write_enable),
.rd_en(fifo_read_enable),
.din(fifo_data_in),
.dout(fifo_data_out),
.full(fifo_full),
.empty(fifo_empty),
);

You get this error: "Error: ordered port connections cannot be mixed with named port connections". I got this when I first started using Vivado a few months back and spent an hour or two trying to figure out what was wrong with my naming or the ports list. Then I wondered if the last comma was the problem and took away, like:

 

i2c_fifo fifo (
.srst(reset | clear),
.clk(clock),
.wr_en(fifo_write_enable),
.rd_en(fifo_read_enable),
.din(fifo_data_in),
.dout(fifo_data_out),
.full(fifo_full),
.empty(fifo_empty)
);

 

NOTE: the lack of a comma after .empty(fifo_empty)

This is correct but the error is very misleading.

1 Solution

Accepted Solutions
peadard
Moderator
Moderator
2,517 Views
Registered: ‎02-07-2008

@dpaul24, @inflector, I reproduced the issue and have documented it in AR# 70145. The AR needs to go through the formal publishing process before it will be available on xilinx.com.

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4 Replies
dpaul24
Scholar
Scholar
1,899 Views
Registered: ‎08-07-2014

This is a perception issue.

 

I find no problem with the message "You get this error: "Error: ordered port connections cannot be mixed with named port connections".

 

Whenever I get such a msg, I would look at my port connections, and the extra comma would be outright visible. Actually I am much more cautious, so that I don't have to rely on tool messages to debug my code. I will write the instiantiation like this. Your chances of mistake are greatly reduced! :-)

 

i2c_fifo fifo (
.srst(reset | clear)      ,
.clk(clock)               ,
.wr_en(fifo_write_enable) ,
.rd_en(fifo_read_enable)  ,
.din(fifo_data_in)        ,
.dout(fifo_data_out)      ,
.full(fifo_full)          ,
.empty(fifo_empty)
);

 

And yes I use Notepad++, which is a great ext editor!

 

Working for a small company, I think many engineers like me are too much dependent on Vivado to get their projects going on time. We really don't have much to say. Even if such things are reported, as I have been seeing from 2014, no one here cares much!

 

------------FPGA enthusiast------------
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peadard
Moderator
Moderator
2,518 Views
Registered: ‎02-07-2008

@dpaul24, @inflector, I reproduced the issue and have documented it in AR# 70145. The AR needs to go through the formal publishing process before it will be available on xilinx.com.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

cleonjones
Visitor
Visitor
1,515 Views
Registered: ‎10-16-2012

Another way to get this error message (in Verilog) is to forget the period in front of the port during assignment:

 

i2c_fifo fifo (
   srst(reset)              , // BAD, should be .srst(reset)
   clk(clock)               , // etc
   wr_en(fifo_write_enable) ,
   rd_en(fifo_read_enable)  ,
   din(fifo_data_in)        ,
   dout(fifo_data_out)      ,
   full(fifo_full)          ,
   empty(fifo_empty)
);

I agree the error message could be a bit more helpful.

 

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nikkimarrow
Newbie
Newbie
816 Views
Registered: ‎03-13-2019

thank you.

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