Mismatch between AXI front door write and backdoor_memory_read
I am using 2018.2 Vivado and have the Xilinix AXI slave VIP integrated in the testbench.
When the DUT (master) does a (front door) write and read to a address location, the write and read values match. But, from the TB when I use "backdoor_memory_read" to read the address written by the DUT, the read back value is a random value and is NOT the value the DUT wrote. The DUT is not doing any address translation.
Any idea why do I see a mis-match between front door write and backdoor read of the same address location?