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Newbie d.subbanna
Registered: ‎01-30-2019

Mismatch between AXI front door write and backdoor_memory_read


I am using 2018.2 Vivado and have the Xilinix AXI slave VIP integrated in the testbench. 

When the DUT (master) does a (front door) write and read to a address location, the write and read values match. But, from the TB when I use "backdoor_memory_read" to read the address written by the DUT, the read back value is a random value and is NOT the value the DUT wrote. The DUT is not doing any address translation. 

Any idea why do I see a mis-match between front door write and backdoor read of the same address location?






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Registered: ‎03-31-2016

Re: Mismatch between AXI front door write and backdoor_memory_read

I would have to go digging through our code to be sure but I believe the backdoor tasks are are interface width addresses but AXI is byte addressed.

That is with a 64-bit AXI the address of 0x10 is backdoor address 2.  This would probably be because the backdoor doesn't have the ability to write less than the interface width.

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