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Visitor pawpaw
Registered: ‎09-05-2017

Missing IP source files with simulator language set to Verilog

We have a custom IP core built from only verilog source files. They are added in the IP packager (File Groups -> Standard -> Simulation) with a xilinx_anylanguagebehavioralsimulation file group name assigned automatically.


Running a behavioral simulation with mixed language set generates the compilation script properly (report_compile_order -used_in simulation even lists it as verilog). However setting the simulator language to verilog effects in the IP completely missing (both from the script and the report_compile_order output). Is there some other option I could use in order to make Vivado recognize these source files as a verilog behavioral model?


I understand a verilog behavioral model for some of the Xilinx cores is not available so it's clear why they are missing in such case. I don't see why our custom IP core expresses such behavior though.


The simulation is being run before synthesis, after generating output products.


Thanks in advance for any input.

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