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Participant scmicron
Participant
2,099 Views
Registered: ‎08-23-2017

Missing ports in AXI VIP

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Dear all,

 

I am using AXI VIP to verify our AXI4 Full Slave peripheral. I generated the VIP design example, and then modified the generated files to suit my needs. However, I can see that the VIP (configured as Master) does not have the following ports: ARSIZE and AWSIZE.

 

Why? How is it able to determine the size of each beat? How am I supposed to add it?

 

Many thanks

Cheers

 

Simone

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1 Solution

Accepted Solutions
Moderator
Moderator
3,903 Views
Registered: ‎11-09-2015

Re: Missing ports in AXI VIP

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Hi @scmicron,

 

Are you sure the VIP has been configured as full AXI4?

 

Try not to use the Auto configuration in the VIP GUI. Try to force it in manual.

 

PS: I didn't had time to work on your other issue yesterday. I will do it today.

 

Regards,

 

Florent

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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2 Replies
Moderator
Moderator
3,904 Views
Registered: ‎11-09-2015

Re: Missing ports in AXI VIP

Jump to solution

Hi @scmicron,

 

Are you sure the VIP has been configured as full AXI4?

 

Try not to use the Auto configuration in the VIP GUI. Try to force it in manual.

 

PS: I didn't had time to work on your other issue yesterday. I will do it today.

 

Regards,

 

Florent

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Participant scmicron
Participant
2,078 Views
Registered: ‎08-23-2017

Re: Missing ports in AXI VIP

Jump to solution

Hi Florent!

 

Good to hear ;)

 

I checked and indeed this problem is due to the wrong settings in the GUI.

 

Thanks

Cheers

 

Simone

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