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Registered: ‎08-18-2011

Mixing post fit and behavioural simulation

I have a very large design in a Virtex 6 FPGA which is connected to a coolrunner II CPLD


I can simulate the CPLD with Post Fit timing but the full FPGA post route timing simulation will take eons to run.


Is there any way for me to drive the CPLD post fit model with the behavioural model out of the FPGA [the block is only 150lines of vhdl]


or can I somehow get a post place and route model of just the module i'm interested in - and then get that into the CPLD testbench?

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