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Adventurer
Adventurer
7,249 Views
Registered: ‎12-09-2010

Monitor signals in mixed VHDL/Verilog environments in Verilog testbench

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Hello,

 

I have a testbench where the testbench is written in Verilog and my component is written in VHDL. The hierarchy looks like this:

Testbench (Verilog)

|- Block design

  |- Component (VHDL)

 

I've tried to access the signal using the hierarchical name but this will generate the following error:

Cross Language Hierarchical name(ssram_if_bfm_tb.inst_ssram_if.ssram_if_tb_i.ssram_if_top_0.U0.blk_ssram_data_mirror.inst_data_mirror.inst_synchronous_fifo.cnt) is not supported in this context. 

Is there a way to monitor the signal from within my testbench?

 

 

Regards

Martin

 

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Moderator
Moderator
11,912 Views
Registered: ‎04-17-2011

Re: Monitor signals in mixed VHDL/Verilog environments in Verilog testbench

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There are few limitation when using Mixed language simulation.
A Verilog hierarchical reference cannot refer to a VHDL unit nor can a VHDL expanded or selected name refer to a Verilog unit.

However, Verilog units can traverse through an intermediate VHDL instance to go into another Verilog unit using a Verilog hierarchical reference.

Details can be seen in page 159, http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug900-vivado-logic-simulation.pdf
Regards,
Debraj
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2 Replies
Moderator
Moderator
11,913 Views
Registered: ‎04-17-2011

Re: Monitor signals in mixed VHDL/Verilog environments in Verilog testbench

Jump to solution
There are few limitation when using Mixed language simulation.
A Verilog hierarchical reference cannot refer to a VHDL unit nor can a VHDL expanded or selected name refer to a Verilog unit.

However, Verilog units can traverse through an intermediate VHDL instance to go into another Verilog unit using a Verilog hierarchical reference.

Details can be seen in page 159, http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug900-vivado-logic-simulation.pdf
Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Adventurer
Adventurer
7,220 Views
Registered: ‎12-09-2010

Re: Monitor signals in mixed VHDL/Verilog environments in Verilog testbench

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Hi Debraj,

 

thank you for your explanation! Too bad this isn't supported.

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