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Newbie mich.mech
Newbie
728 Views
Registered: ‎03-01-2018

New to Verilog . (Code help/tips for new verilog programmer)

Jump to solution

I am trying to simulate a 4-bit addition subtraction unit. I have tested the full adder module and I know that it works. However I can not seem to put the code together into the four bit ripple carry add/subtract er.(the code simulates but does not output correct values through my test bench.) 

What am i doing wrong/badly as I am very new to verilog. (Tips on how to debug...etc)

 

  //Full adder

`timescale 1ns / 1ps

`default_nettype none

 

module full_adder(S,Cout,A,B,Cin);

input wire A,B,Cin;

output wire S, Cout;

assign S = A^B^Cin;

assign Cout =(A & B|B & Cin)|Cin&A;

 

endmodule


// Adder subtracter.

`timescale 1ns / 1ps

`default_nettype none

 

module add_sub( Sum,Overflow,opA,opB,opSel);

output wire [3:0] Sum;

output wire Overflow;

input wire [3:0] opA, opB;

input wire opSel;

 

wire [3:0] notB;

wire c0, c1, c2, c3;

 

assign notB[0] = (opB[0] ^ opSel);

assign notB[1] = (opB[1] ^ opSel);

assign notB[2] = (opB[2] ^ opSel);

assign notB[3] = (opB[3] ^ opSel);

 

full_adder adder0(Sum[0],c0,opA[0],notB[0],opSel);

full_adder adder1(Sum[1],c1,opA[0],notB[0],c0);

full_adder adder2(Sum[2],c2,opA[0],notB[0],c1);

full_adder adder3(Sum[3],c3,opA[0],notB[0],c2);

 

assign Overflow = c2 ^c1;

endmodule


//test bench

`timescale 1ns / 1ps

`define STRLEN 32

`define NUM_TESTS 32

 

/*This test bench is full of non-synthesizable constructs, which basically means it is

*restricted to simulation only!*/

module add_sub_tb;

 

  

  /*This  task simply checks the output of our circuit against a

known answer and prints a message based on the outcome. Additionally,

this task increments the variable we are using to keep track of the

number of tests successfully passed.*/

  task passTest;

   input [4:0] actualOut, expectedOut;

   input [`STRLEN*8:0] testType;

   inout [7:0] passed;

   

   if(actualOut == expectedOut) begin $display ("%s passed", testType); passed = passed + 1; end

   else $display ("%s failed: %x should be %x", testType, actualOut, expectedOut);

   endtask

   

/*this task simply informs the user of the final outcome of the test*/

   task allPassed;

   input [7:0] passed;

   input [7:0] numTests;

  

   if(passed == numTests) $display ("All tests passed");

   else $display("Some tests failed");

   endtask

 

   // Inputs

   reg [3:0] opA;

   reg [3:0] opB;

   reg opSel;

   

/*known answer signals*/

reg [3:0] Result_check;

reg Overflow_check;

reg [7:0] passed;

 

   // Outputs

   wire [3:0] Sum;

wire Overflow;



   // Instantiate the Unit Under Test (UUT)

   add_sub uut (

   .Sum(Sum),

    .Overflow(Overflow),

   .opA(opA),

   .opB(opB),

   .opSel(opSel)

   );

 

   initial begin

   // Initialize Inputs

   opA = 0;

   opB = 0;

   opSel = 0;

    passed = 0;

   

    // Add stimulus here   

    repeat(`NUM_TESTS)//do `NUM_TESTS times over...

      begin

        /*compute expected result*/

        if(opSel) //if subtract

          begin

            Result_check = opA - opB;

            Overflow_check = ((opA[3] & ~opB[3] & ~Result_check[3]) | (~opA[3] & opB[3] & Result_check[3]));

          end

        else //if add

          begin

            Result_check = opA + opB;

            Overflow_check = ((opA[3] & opB[3] & ~Result_check[3]) | (~opA[3] & ~opB[3] & Result_check[3]));

          end

      

        #10; //delay! basically wait 10 time units

        /*perform a known answer test*/

        passTest({Overflow, Sum}, {Overflow_check, Result_check}, "Addition/Subtraction Unit Test", passed);

        /*generate a new random set of inputs  sort of a Monte Carlo simulation!*/

        opA = $random;

        opB = $random;

        opSel = $random;

      end

    /*check to see if all tests passed*/

    allPassed(passed, `NUM_TESTS);

    $stop; //hault simulation cause we are done!

   end

endmodule

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1 Solution

Accepted Solutions
Scholar markcurry
Scholar
939 Views
Registered: ‎09-16-2009

Re: New to Verilog . Code help

Jump to solution

 

Hint - hit that preview button before posting.

 

I did parse at least your first few sentences.  First, don't post code YET.  Describe the problem better. You state "I can not seem to put the code together into the four bit ripple carry add/subtracter"

 

What do you mean here?  Does it simulate at all?  Does it pass syntax checks?  Or is it simulating incorrectly?  If it's simulating incorrectly what steps did you take to debug?

 

You'd also be surprised how often you answer your own question by just taking a step back, and describing the problem. I'm still shocked how many times I solved a problem on my own by just describing the problem too one of my colleagues... 

 

That's also fun from the other side - silently listen to a coworker describe a problem... Seeing the light bulb go off, co-worker goes away having solved themselves.  Fun to state "glad I could help" having done nothing but listen...

 

Regards,

 

Mark

1 Reply
Scholar markcurry
Scholar
940 Views
Registered: ‎09-16-2009

Re: New to Verilog . Code help

Jump to solution

 

Hint - hit that preview button before posting.

 

I did parse at least your first few sentences.  First, don't post code YET.  Describe the problem better. You state "I can not seem to put the code together into the four bit ripple carry add/subtracter"

 

What do you mean here?  Does it simulate at all?  Does it pass syntax checks?  Or is it simulating incorrectly?  If it's simulating incorrectly what steps did you take to debug?

 

You'd also be surprised how often you answer your own question by just taking a step back, and describing the problem. I'm still shocked how many times I solved a problem on my own by just describing the problem too one of my colleagues... 

 

That's also fun from the other side - silently listen to a coworker describe a problem... Seeing the light bulb go off, co-worker goes away having solved themselves.  Fun to state "glad I could help" having done nothing but listen...

 

Regards,

 

Mark