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Observer 4a4ik
Registered: ‎03-29-2017

Non project mode, post synthesis simulation, tooks longer time in new VIVADO versions

I have a problem with post synthesis simulation for my project, I use non project mode (xvhdl, xelab, xsim):

with VIVADO 2016.4 it works fine (i use xsim from 2016.4 folder) (attached 1.png)

with 2017.4 OR 2018.2, it takes about 5x longer time to finish and RAM usage continues to rise (attached 2.png), (I have seen RAM problem on the forums),

with 2018.3, it takes about 5x longer time to finish (RAM is okay) (attached 3.png).

With VIVADO GUI or project mode everything works fine.

Elaborated simulation works fine.


So I have created a new, smaller project that consist of 1 shift register (attached sim2.rar). But the problem remained.

I have tested VIVADO on win 7 and win 10 with different machines.

Tried direct instantiation and component instantiation (VHDL).

Tried reinstalling VIVADO on C disk.

No luck so far


Is there something I am missing, or is it VIVADO problem?





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