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Observer eniv4
Observer
8,802 Views
Registered: ‎05-17-2012

OBUFDS cell behaves obscurely in Place and Route simulation

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Hi,

 

I am running a timing simulation generated from post-place and route model. The model includes a ddr lvds IO, which instantiates an OSERDES along with an OBUFDS cell.

 

The OSERDES is clocked with a 200MHz and 400MHz clocks and seems to be working fine. The output of the OSERDES, TQ, is routed to an OBUFDS cell.

 

The problem is that the OBUFDS outputs a constant 0 in spite of the changing input, which is the TQ wire from OSERDES. The problem does not exist in behavioral simulation.

 

Following is the ddr_lvds_io code:

 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

ENTITY ddr_lvds_io IS
PORT (
      d1                    : IN STD_LOGIC;    -- clock 0 rising edge
      d2                    : IN STD_LOGIC;    -- clock 0 falling edge
      d3                    : IN STD_LOGIC;    -- clock 1 rising edge
      d4                    : IN STD_LOGIC;    -- clock 1 falling edge
        dout_dpp            : OUT STD_LOGIC;
        dout_dpn       : OUT STD_LOGIC;
      clk2X                : IN STD_LOGIC;    -- freq=2x
        clk1X         : IN STD_LOGIC;    -- freq=x
      reset          : IN STD_LOGIC
      );
END ddr_lvds_io;


ARCHITECTURE Behavioral  OF ddr_lvds_io IS

SIGNAL      dout                       : STD_LOGIC;

BEGIN
        

            
    OSERDES_TX_DATA_d : OSERDES
      GENERIC MAP(
          DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 4,
          INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER",
          SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 4)

        PORT MAP (
            OQ => dout,
            SHIFTOUT1 => open,
            SHIFTOUT2 => open,
            TQ => open,
            CLK => clk2X,
            CLKDIV => clk1X,
            D1 => d1,
            D2 => d2,
            D3 => d3,
            D4 => d4,
            D5 => '0',
            D6 => '0',
            OCE => '1',
            REV => '0',
            SHIFTIN1 => '0',
            SHIFTIN2 => '0',
            SR => reset,
            T1 => '0',
            T2 => '0',
            T3 => '0',
            T4 => '0',
            TCE => '0');   
    
    obuftds_inst_dvalid : obufds
    GENERIC MAP (
        iostandard => "LVDS_25")
        PORT MAP (
            o  => dout_dpp,   -- diff_p output (connect directly to top-level port)
            ob => dout_dpn,   -- diff_n output (connect directly to top-level port)
            i  => dout    -- buffer input
            );

END Behavioral;

 

 

Any support would be much appreciated.

 

Thanks in advance.

-Eyal

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
10,086 Views
Registered: ‎07-16-2008

Re: OBUFDS cell behaves obscurely in Place and Route simulation

Jump to solution

@eniv4 wrote:

Graces,

I checked the sdf file and the maximum IOPATH delay associated with that instance of OBUFDS is 1548ps:

  (CELL (CELLTYPE "X_OBUFDS")
    (INSTANCE i_appsfpga_io\/clk_io_a\/obuftds_inst_dvalid\/OBUFDS)
      (DELAY
        (ABSOLUTE
          (PORT I ( 0 ))
          (IOPATH I O (1417:1548:1548))
          (IOPATH I OB (1417:1548:1548))
        )
      )
  )

 

This can explain the problem since the input to the OBUFDS cell is a 400MHz signal, which means that pules are 1.25ns = 1250ps wide. I haven't tried the suggested solution yet, however, I'm using ISE13.4, and this issue should have been addressed on ISE12.1.

 


A workaround is to manually modify the SDF to add  PATHPULSE value, so as to prevent pulse swallowing.

e.g.

  (CELL (CELLTYPE "X_OBUFDS")
    (INSTANCE i_appsfpga_io\/clk_io_a\/obuftds_inst_dvalid\/OBUFDS)
      (DELAY

        (PATHPULSE (104))
        (ABSOLUTE
          (PORT I ( 0 ))
          (IOPATH I O (1417:1548:1548))
          (IOPATH I OB (1417:1548:1548))
        )
      )
  )


 

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-------------------------------------------------------------------------

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19 Replies
Xilinx Employee
Xilinx Employee
8,783 Views
Registered: ‎01-03-2008

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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Your post is confusing as you mentioned TQ multiple times and you named the OBUFDS instance with a T, but the code does not use TQ. Can you please clarify?

One possibly reason, is the reset input held high?
------Have you tried typing your question into Google? If not you should before posting.
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Observer eniv4
Observer
8,777 Views
Registered: ‎05-17-2012

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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Thanks a lot for the response.

 

You are obviously right about the misleading name of the OBUFDS instance and the inclarity about the output port TQ. Nonetheless, the problem still exist.

 

As seen from the code I attached earlier, I was mistakenly referreing to TQ instead of OQ. OQ which is the the data path output of the OSERDES cell is routed to the input of the OBUFDS under a signal named "dout". While "dout" seems to be toggling as expected, under the name OSERDER_TX_DATA_d /OQ  or obuftds_inst_dvalid/OBUFDS /I  which are similiar, the output of the OBUFDS cell named obuftds_inst_dvalid/OBUFDS /O is not.

 

Reset at this stage is low as you can see on the OSERDER_TX_DATA_d /SR  port
.

I have attacjed a screenshot along hiererachy names (The top 5 signals are relevant):

 

 

Thanks again.

-Eyal

OBUFDS_screenshot.png
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Teacher eteam00
Teacher
8,767 Views
Registered: ‎07-21-2009

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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My questions are syntax-related, based mostly on a distinct ignorance of VHDL --

 

  • Is VHDL case sensitive?  The OSERDES instantiation port names are all uppercase, while the OBUFDS instatiation uses lowercase port names.
  • Do you need to be concerned about upper/lower case consistency between sim window and source code?

 

-- Bob Elkind

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Summary:
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Observer eniv4
Observer
8,760 Views
Registered: ‎05-17-2012

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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Hello Bob,

 

Thanks for showing interest in my question.

 

1.VHDL is case insensitive.

2.Since this is a post place-and-route simulation, only the uppercase O,OB and I ports of the OBUFDS primitive appear in the design.  I have also checked the connectivity using the technology schematic viewer (See attached).

 

Thanks again.

-Eyal

 

 

OBUFDS_schematic.png
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Xilinx Employee
Xilinx Employee
8,746 Views
Registered: ‎07-16-2008

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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From your description, it could be a pulse swallow issue, as it doesn't appear in behavioral simulation.

Check this answer.

http://www.xilinx.com/support/answers/34577.htm

-------------------------------------------------------------------------
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-------------------------------------------------------------------------
Xilinx Employee
Xilinx Employee
8,741 Views
Registered: ‎01-03-2008

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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That shouldn't happen with a 400 Mbps data rate. Have you checking the simulation compilation for any errors or warnings?
------Have you tried typing your question into Google? If not you should before posting.
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Observer eniv4
Observer
8,732 Views
Registered: ‎05-17-2012

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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Graces,

I checked the sdf file and the maximum IOPATH delay associated with that instance of OBUFDS is 1548ps:

  (CELL (CELLTYPE "X_OBUFDS")
    (INSTANCE i_appsfpga_io\/clk_io_a\/obuftds_inst_dvalid\/OBUFDS)
      (DELAY
        (ABSOLUTE
          (PORT I ( 0 ))
          (IOPATH I O (1417:1548:1548))
          (IOPATH I OB (1417:1548:1548))
        )
      )
  )

 

This can explain the problem since the input to the OBUFDS cell is a 400MHz signal, which means that pules are 1.25ns = 1250ps wide. I haven't tried the suggested solution yet, however, I'm using ISE13.4, and this issue should have been addressed on ISE12.1.

 

Mcgett,

I always go over the warnings I get from the tools. I haven't found anything suspicous. It there something in particular I should be looking for?

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Xilinx Employee
Xilinx Employee
8,723 Views
Registered: ‎01-03-2008

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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I missed that you had set the DDR attribute on the OSERDES, so it is 800 Mbps and not 400 Mbps that I had assumed with a 1.25nS bit time.   Since this is shorter than the delay through the OBUF it is subject to pulse swallowing.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Observer eniv4
Observer
8,718 Views
Registered: ‎05-17-2012

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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Thanks.

 

Wasn't that suppose to had a fix on ISE13.4

 

Will adding the pathpulse constuct to the annotation harm the similarty between the timing simulation and the real FPGA design?

 

-Eyal

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Xilinx Employee
Xilinx Employee
7,443 Views
Registered: ‎01-03-2008

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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> Wasn't that suppose to had a fix on ISE13.4

 

The answer record said to add "specify pathpulse .001" to the iSim TCL command and yes it said that the swallowing issue was resolved in 12.1.    However, it isn't clear to me why the default behavior of iSim would have changed in the first place so this may have been reverted in a later release.

 

Early simulator had a concept of TRANSPORT and INERTIAL delay types and the default behavior for Verilog simulators should be INERTIAL according to a quick Google search.  With INERTIAL delays any pulse that is less than the delay time will be swallowed/eliminated while TRANSPORT delays will have pass any pulse. 

 

In real hardware there is a mix of these two events where delays below a certain time threshold will be swallowed/eliminated.  Control for this threshold appears to have been added to the SDF specification at some point before 1995 with the addition of PATHPULSE and PATHPULSEPERCENT properties.  I am not an iSim expert, but the TCL command is likely intended to override the default value and/or SDF values and likely would be required to be set after the SDF file has been read into the simulator.

 

I know that this isn't a definitive answer, but hopefully it helps.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Observer eniv4
Observer
7,430 Views
Registered: ‎05-17-2012

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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Thanks!

 

I have tried to set the global path pulse reject to .001, but that still does not work.

Any other TCL commands or ideas I can try?

 

-Eyal

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Xilinx Employee
Xilinx Employee
7,421 Views
Registered: ‎01-03-2008

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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Could you post the simulation log file?

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Observer eniv4
Observer
7,416 Views
Registered: ‎05-17-2012

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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Thanks again for trying to help.

 

This is the contents of the isim.log file:

 

ISim log file
Running: C:\Users\Eyal\Documents\FPGA\TransMat\DDC4100\APPSFPGA_TRANSMAT2\appsfpga_tb_isim_par.exe -intstyle ise -gui -tclbatch isim.cmd -view C:/Users/Eyal/Documents/FPGA/TransMat/DDC4100/APPSFPGA_TRANSMAT2/timesim.wcfg -wdb C:/Users/Eyal/Documents/FPGA/TransMat/DDC4100/APPSFPGA_TRANSMAT2/appsfpga_tb_isim_par.wdb
ISim O.87xd (signature 0xc3576ebc)
This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# run 20000ns
Simulator is doing circuit initialization process.
INFO: SDF backannotation was successful with SDF file netgen/par/appsfpga_timesim.sdf, for root module /appsfpga_tb/uut/.
Finished circuit initialization process.

 

-Eyal

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Xilinx Employee
Xilinx Employee
10,087 Views
Registered: ‎07-16-2008

Re: OBUFDS cell behaves obscurely in Place and Route simulation

Jump to solution

@eniv4 wrote:

Graces,

I checked the sdf file and the maximum IOPATH delay associated with that instance of OBUFDS is 1548ps:

  (CELL (CELLTYPE "X_OBUFDS")
    (INSTANCE i_appsfpga_io\/clk_io_a\/obuftds_inst_dvalid\/OBUFDS)
      (DELAY
        (ABSOLUTE
          (PORT I ( 0 ))
          (IOPATH I O (1417:1548:1548))
          (IOPATH I OB (1417:1548:1548))
        )
      )
  )

 

This can explain the problem since the input to the OBUFDS cell is a 400MHz signal, which means that pules are 1.25ns = 1250ps wide. I haven't tried the suggested solution yet, however, I'm using ISE13.4, and this issue should have been addressed on ISE12.1.

 


A workaround is to manually modify the SDF to add  PATHPULSE value, so as to prevent pulse swallowing.

e.g.

  (CELL (CELLTYPE "X_OBUFDS")
    (INSTANCE i_appsfpga_io\/clk_io_a\/obuftds_inst_dvalid\/OBUFDS)
      (DELAY

        (PATHPULSE (104))
        (ABSOLUTE
          (PORT I ( 0 ))
          (IOPATH I O (1417:1548:1548))
          (IOPATH I OB (1417:1548:1548))
        )
      )
  )


 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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Observer eniv4
Observer
7,405 Views
Registered: ‎05-17-2012

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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Thanks. That worked!

 

Any TCL command that I can use with ISIM which will affect all instances of the X_OBUFDS cell?

 

-Eyal

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Observer eniv4
Observer
7,402 Views
Registered: ‎05-17-2012

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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BTW, why did you choose 104ps ?
Thanks again
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Xilinx Employee
Xilinx Employee
7,396 Views
Registered: ‎07-16-2008

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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The value is randomly selected based in the PATHPULSE value of X_BUF in my example design.

You might as well specify a much lower value.

 

I'm not able to find any ISIM Tcl command or option that can specify the pulse width.

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Observer eniv4
Observer
7,390 Views
Registered: ‎05-17-2012

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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Thanks for everyone's help.

 

-Eyal

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Observer mik3l3_hdl
Observer
257 Views
Registered: ‎08-15-2019

Re: OBUFDS cell behaves obscurely in Place and Route simulation

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Hi guys,

 

so my platform is :

Ultrascale+ vcu118  and Vivado 2018.2.

I am implementing an ODDR module which wraps inside it a bounch of OSERDE3 each one in series with an OBUFDS.

Without this wrap, the OBUFDS output ports can be constrained as LVDS

while with the wrap the output ports are considered single ended by the placer and the LVDS is marked in red (in the I/O planning tab) and cannot be used.

 

How i can use the wrap and keeping the IO standard  of the ports  to be LVDS?

 

Thanks

Regards

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