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Visitor
Visitor
451 Views
Registered: ‎05-25-2019

ODDR2 doesn't work?!

Hi

I Write a SDRAM Controller program and use ODDR2 Primitive in it. I set everything correctly and checked it with Xilinx User Guide and Other Questions in Xilinx Forum. But ODDR2 Hasn't any output in ISIM Simulation. Can you help me?

ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE",-- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => sdram_clk, -- 1-bit output data
C0 => clk_top, -- 1-bit clock input
C1 => nclk_top, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);

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ODDR2_Simulation.jpg
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Xilinx Employee
Xilinx Employee
406 Views
Registered: ‎07-16-2008

What is the waveform of the ODDR2 primitive signals like? You can find the ODDR2 hierarchy and add the signals to wave.

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Visitor
Visitor
372 Views
Registered: ‎05-25-2019

Yes, I Exactly do that. My primary Signals are "clk_top" for "C0" and "nclk_top" for "C1". You can see the signals and their waveform on the attached simulation output picture.

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Xilinx Employee
Xilinx Employee
340 Views
Registered: ‎07-16-2008

No, I would like to see how the internal signals connected to the ODDR primitive toggle. The 'clk_top' and 'sdram_clk' are both top level ports. There'll be input/output IO buffer between the ODDR and the ports.

Can you please attach the test case?

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