01-07-2019 10:53 PM
I instantiate a RAMB32E1 primitive in my design, and set :
2) WRITE_WIDTH_B=18, READ_WIDTH_B=18; // write port
3) WRITE_WIDTH_A=4, READ_WIDTH_A=4; // read port
Then, i simulate my design with ISIM, the simulation result is right, the read datas are the same as the written datas,but a DRC error exists :
DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 72 when RAM_MODE = SDP
Then i try to change READ_WIDTH_A to 72, but the read datas are not my needed.
So, is it a bug ?
01-09-2019 01:35 AM
How do you expect port A to map to port B? They do not map properly
If the widths are different, you need to have one port a multiple of the other. So with Port B = 18 bits, Port A can only be 9 bits.
If Port B is 16, then port A can be 1/2/4/8/16/32 bits.
02-21-2019 07:47 PM
Thanks for your reply.
1. The valid values for Read Widthand Write Width attritutes are 0,1,2,4,9,18,36, there are no 8,16,32;
2. My doubt is why WRITE_WIDTH_B or READ_WIDTH_A must set to 72 when RAM_MODE = SDP ?
3. If i want to write 16bits and read 4bits in SDP mode, how should i set WRITE_WIDTH_B, READ_WIDTH_B, WRITE_WIDTH_A, READ_WIDTH_A attributes ?
4 I simulate the same code in vivado, there are no drc errors.