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Explorer
Explorer
1,872 Views
Registered: ‎04-01-2016

PLL / MMCM simulation

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Hi all,

 

I googled for the solution but didn't find anything for my question which is a very common issue I assume.

 

I do have several MMCMs in my design. Simulation is done with Cadence. Now of course I want to simulate all the different clock domains. I didn't found any simulation model for the clock managers. So I made simulation models on my own. The problem is that if some clocks change in frequency I have to adapt the simulation model.

 

For example one of my simulation models is:

 

2018-09-27_08h40_10.png

 

I think this is not the best way to do the simulation of the PLLs / MMCMs. Can anyone provide me a better solution? And is the solution "lightweight", meaning that I can skip the settling time of the PLL and directly can start simulating with "PLL_LOCKED = TRUE"?

 

Thanks in advance!

Sebastian

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Moderator
Moderator
1,817 Views
Registered: ‎02-09-2017

Hi @sebastian_z,

 

So what you need is the testbench for the MMCM/PLL simulation?

 

Vivado does create it for you. After you used the Clocking Wizard and the IP is created, you need to right-click on the IP xci file under the Sources tab and select "Open IP Example Design".

 

In there you will have all the resources for simulating and even implementing the project.

 

I just did that and got the following:

clocking_wizard_testbench.JPG

clocking_wizard_simulation.JPG

 

In this example, just for testing, I configured the MMCM to receive a 100MHz input clock and a 200MHz and 300MHz output clocks.

 

Please also find attached the generated testbench for reference, but I encourage you to generate your own trough Vivado.

 

 

Andre Guerrero

Product Applications Engineer

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Voyager
Voyager
1,858 Views
Registered: ‎08-16-2018

"if some clocks change in frequency" - that's what a PLL is for, to keep the frequency constant.

If what you want to simulate is the jitter, you can modulate (for example, sinusoidal) the clock's period. Whether this reflects reality or is just a mathematical exercise, you need the MMCM's PLL control model and parameters, if Xilinx are so kind to share with you...

If what you want to simulate is a discrete frequency change, you can modify your CLK_PERIOD variables, don't define them as constant. You will still miss the transient.

In short, what exactly do you want to simulate? Not only what signal/ behaviour but also at what level? logical, electrical? There is no single model/ simulation that answers all questions, at least for non trivial situations.

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Explorer
Explorer
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Registered: ‎04-01-2016

@johnvivm: Thanks for the hints, I was a bit unspecific.

 

With changing the frequency, I mean the following: the system architects several times realized that the frequency has to be changed. This means not the jitter but the real frequency, e.g. one was changed from 20 MHz to 10 MHz. In the IP core this is done fast and no problem. But it is possible that I or another team member forgets changing the frequency in the simulation model. And then we could spent hours to search the error which occurs because of the wrong simulation model.

 

So what I really want to do is simulation on a logical level.

 

Kind regards

Sebastian

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Voyager
Voyager
1,843 Views
Registered: ‎08-16-2018

We all forget things. That's what ECO (Engineering Change Order) are for. 

I still don't get why do you need to simulate a multiclock domain. If properly done, it will work whatever the frequencies are, the only think you have to care about is buffer size, but you don't need to simulate anything for that. Unless you have odd signals...

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Explorer
Explorer
1,837 Views
Registered: ‎04-01-2016

The problem is that I of course have to write a testbench. And for that I use the simulation dummy which generates the frequency but not the sources from Xilinx itself.

So if I change frequency in the Vivado toolchain I have to change it in the MMCM simulation dummy as well and this is what I don't want because it is error prone.

 

So what I'm asking is, if Xilinx provides sources for that. For the EBR the simulation sources are included in the generated IP core directory. This is not true for the MMCMs / PLLs.

 

Kind regards

Sebastian

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Highlighted
Moderator
Moderator
1,818 Views
Registered: ‎02-09-2017

Hi @sebastian_z,

 

So what you need is the testbench for the MMCM/PLL simulation?

 

Vivado does create it for you. After you used the Clocking Wizard and the IP is created, you need to right-click on the IP xci file under the Sources tab and select "Open IP Example Design".

 

In there you will have all the resources for simulating and even implementing the project.

 

I just did that and got the following:

clocking_wizard_testbench.JPG

clocking_wizard_simulation.JPG

 

In this example, just for testing, I configured the MMCM to receive a 100MHz input clock and a 200MHz and 300MHz output clocks.

 

Please also find attached the generated testbench for reference, but I encourage you to generate your own trough Vivado.

 

 

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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Explorer
Explorer
1,810 Views
Registered: ‎04-01-2016

Hi @anunesgu

 

I will try that out! Thanky you very much for helping! This is exactly what I was looking for!

 

Kind regards

Sebastian