04-21-2020 03:51 AM
I would like to partially simulate a block design. The problem I have is that vivado cannot find the IP-core (see picture below).
How can I write a testbench and simulate for example only one IP-core? Why are the IP-Cores not visible in my IMU_testbench.vhd?
04-27-2020 03:45 AM
@amuniox thank you for your reply. I declared the component as it should be:
component zsys_blk_mem_gen_0_0 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 3 downto 0 ); addra : in STD_LOGIC_VECTOR ( 31 downto 0 ); dina : in STD_LOGIC_VECTOR ( 31 downto 0 ); douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 3 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 31 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 31 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ); rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC ); end component zsys_blk_mem_gen_0_0;
This IP core is from my block design and I would like to simulate it in my testbench seperatly (OPU_tb) but the core cannot be found:
I can include the core seperately to my design by making a copy and changing the name from from zsys_blk_mem_gen_0_0 to zsys_blk_mem_gen_0_1 (this core is now not part of my block design):
Now I can simulate it in my testbench but this is not the solution I can work with.
What library has to be included to make all the cores from my block design visible in test benches that are not including the whole block design?
04-27-2020 03:59 AM
When I include my block design as a component the core can be found within the wrapper for for the block design but not outside of it. Do I have to include my block design as a library and if yes how can I do it?