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Adventurer
Adventurer
12,746 Views
Registered: ‎12-09-2010

Passing strings to tasks in SystemVerilog

Hello,

 

I have a task which expects a string as input. When I write the task like this:

  task automatic t_assert(input condition, input string error_message);
    if(!(condition))
      $display("Error message: %s", error_message);
      $finish(2);
  endtask

 I get an error message that the string data type is not yet supported for simulation (Vivado 2014.1).

When I write the task like this:

  task automatic t_assert(input condition, input [1024*8-1:0] error_message);
    if(!(condition))
      $display("Error message: %s", error_message);
      $finish(2);
  endtask

 the output looks like this:

Error message:   

 when the task was called with the following command:

t_assert (1'b0 == 1'b1, "Something went wrong");

 Obviously the string input parameter is missing in my error output message. Can anybody tell me why the string doesn't get printed out?

 

 

Regards

Martin

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6 Replies
Xilinx Employee
Xilinx Employee
12,737 Views
Registered: ‎10-24-2013

Re: Passing strings to tasks in SystemVerilog

Hi,
Vivado simulator doesn't support systemverilog yet.
Refer to page 4 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug937-vivado-design-suite-simulation-tutorial.pdf which says that it supports only verilog & vhdl
Thanks,Vijay
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Adventurer
Adventurer
12,728 Views
Registered: ‎12-09-2010

Re: Passing strings to tasks in SystemVerilog

It doesn't support SystemVerilog fully yet, but part of the language seems to be supported already: Supported SystemVerilog Constructs in Vivado Simulator

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Moderator
Moderator
12,726 Views
Registered: ‎04-17-2011

Re: Passing strings to tasks in SystemVerilog

If you are using Vivado 2014.1, it does support System Verilog now but not if you are using any older version. automatic tasks are supported but this could be a bug. Please post your archived Vivado project so that it can be checked further.
Regards,
Debraj
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Adventurer
Adventurer
12,031 Views
Registered: ‎12-09-2010

Re: Passing strings to tasks in SystemVerilog

I've totally forgot this thread. I've attached an example for you. The type of the source file is set to SystemVerilog but you can change the type to Verilog also. The result is the same in both cases that the string which was given as a parameter to the t_assert task is not shown.

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Xilinx Employee
Xilinx Employee
11,929 Views
Registered: ‎09-13-2014

Re: Passing strings to tasks in SystemVerilog

Few points

 

1> String( dynamic type) is not supported in Vivado simulator. It's planned in near future.

2> Regarding issue, It's not a bug rather issue with use case, let me explain 

 

Your example

 

task automatic t_assert(input condition, input [1024*8-1:0] error_message);
    if(!(condition))
      $display("Error message: %s", error_message);
      $finish(2);
  endtask

Now the input width is 1024 byte and when you are passing a very small string, say 'Failures!', then simulator with print 'Failures!' but it will append 1025 blanck space in front and hence the result will show up at end of a very long line.

 

The best way to do is by replacing '%s' with '%0s' so it won't append blanck space and you will see the desired result.

 

--dhiRAj

 

 

 

 

 

 

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Moderator
Moderator
11,923 Views
Registered: ‎07-21-2014

Re: Passing strings to tasks in SystemVerilog

Hi,

 

Just to add....

 

You can see the string at the right most of the console. Refer below snapshot:

 

Capture.PNG

 

Reduce the size of error_message to see the message properly, use suggestions given by dhiraj to resolve this issue.

 

Thanks,
Anusheel
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