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Contributor
Contributor
9,363 Views
Registered: ‎02-12-2009

Post Implementation Timing Simulation not supported for VHDL?

I noticed in UG900 the following note:

 

Post-Synthesis and Post-Implementation timing simulations are supported for 
Verilog only. There is no support for VHDL timing simulation. If you are a 
VHDL user, you can run post synthesis and post implementation functional 
simulation (in which case no SDF annotation is required and the simulation 
netlist uses the UNISIM library). You can create the netlist using the write_vhdl 
Tcl command. For usage information, refer to the Vivado Design Suite Tcl 
Command Reference Guide (UG835) [Ref 7].

Is this limitation only on the use of Xsim/Vivado Simulator?  

 

If not, this poses a problem for those of us in the Aerospace world where post implementation timing simulations are required for many designs.  Many of us have corporate standards that dictate the use of VHDL.  Vivado is going to have to support post implementation timing simulation for VHDL designs.

 

DornerWorks
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6 Replies
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-07-2015

Re: Post Implementation Timing Simulation not supported for VHDL?

HI @kkoorndyk

 

This will not be an issue if you have a mixed language simulator. (note: Xsim is a mixed language simualtor)
You can write the simulation netlist in verilog  and use that for timing simulation.
write_verilog -mode timesim. 
Refer pg 1447 of tcl ref guide for usage .

Please refer to the following answer record:

http://www.xilinx.com/support/answers/57127.html

Thanks
Bharath
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Contributor
Contributor
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Registered: ‎02-12-2009

Re: Post Implementation Timing Simulation not supported for VHDL?

Understood.  However, Xsim does not provide Code Coverage support so many of us need to use other simulators such as QuestaSim.  The cost of a Mixed-Language license is on the order of $50K versus a VHDL-only license for $25K.  That adds up quick in a large organization needing dozens of these licenses.  This is another reason folks are not happy about the plan to provide IP in Verilog only.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-07-2015

Re: Post Implementation Timing Simulation not supported for VHDL?

Hi @kkoorndyk


I unserstand your concern.
 As of now , using Xsim or third party simulator with mixed laguage support is the only option for performing timing simulations on VHDL designs in Vivado..

if you can elaborate on code coverage support limitations which is prohibiting you from using Xsim. That would be a valuable input to us.

Thanks
Bharath
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Contributor
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Registered: ‎02-12-2009

Re: Post Implementation Timing Simulation not supported for VHDL?

https://en.wikipedia.org/wiki/Code_coverage

 

http://go.mentor.com/2gn5p

 

 

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Scholar
Scholar
9,200 Views
Registered: ‎04-26-2012

Re: Post Implementation Timing Simulation not supported for VHDL?

@nagabhar"As of now , using Xsim or third party simulator with mixed laguage support is the only option for performing timing simulations on VHDL designs in Vivado.."

 

 Is support for the SIMPRIM library in VHDL on Xilinx's internal roadmap?

 

 If not, can you please file a CR requesting this, reasons being:

 

 1)  This is a major regression in capability from ISE.

 

  2) As clearly stated earlier in the thread, this regression prevents users from using a qualified VHDL-only verification flow for performing timing analysis on XIlinx devices.

 

-Brian

 

http://forums.xilinx.com/t5/Simulation-and-Verification/VHDL-Timing-Netlist-Vivado/m-p/597365

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Scholar
Scholar
8,944 Views
Registered: ‎04-26-2012

Re: Post Implementation Timing Simulation not supported for VHDL?

@nagabhar

 

Could you, or someone else from Xilinx, please answer the questions from my August 22 post:

"

"  Is support for the SIMPRIM library in VHDL on Xilinx's internal roadmap?

"

"  If not, can you please file a CR requesting this, reasons being:

"

"  1)  This is a major regression in capability from ISE.

"

"   2) As clearly stated earlier in the thread, this regression prevents users from using a qualified

"        VHDL-only verification flow for performing timing analysis on XIlinx devices.

"

 

-Brian