Post Synthesis Functional Simulation of a Transmitter and Receiver in Vivado.
I am working on an Encoder and Decoder, for a Baseband transmitter and receiver. Both encoder and decoder are working, Vivdao synthesizable. I have created individual test benches for both modules.Behavioral and Post synthesis functional simulation works fine for individual Modules.
Now I would like to perform Post Synthesis Functional simulation of Both Encoder and Detogethereteher. I have created a testbench by instantitaing top-level modules of Encoder and decoder, Behavioral simulation of the system works fine, but post-synthesis simulation doesn't. My question is how can i proceed to cretae a testbench for Post Synthesis Funcctional Simulation of the system.
My question is how can I proceed to create a testbench for Post Synthesis Functional Simulation of the system.
I have created a top-level module, in which I instantiated both encoder and decoder together, but the problem is how can I map output ports of the encoder to the input ports of Decoder?