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Scholar ronnywebers
Scholar
184 Views
Registered: ‎10-10-2014

Post-synthesis simulation shows 100ps shift of a signal instead of 1 clock cycle

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(Using Vivado 2018.2) I have a strange issue when I perform a post-synthesis functional simulation - I can see a strange '100 ps' shift of a signal, instead of 1 clock cycle (which has a period of10ns in my testbench)

first the expected behaviour : I am expecting the AXI_ARVALID signal below to go to '1' exactly1 clock cycle after  AXI_ARVALID = '1'. In the following screenshot of a behavioral simulation, the waveforms are as expected:

read correct.png

now when switching to post-synthesis simulation, I can see the AXI_ARREADY occur earlier :

wrong read.png

when I zoom in on that, I can see that AXI_ARREADY has actually a 100ps delay :

100ps.png

I think to have read on the forum somewhere that this 100ps is because of some race condition in my simulation. The 100ps is a way of the simulator to show a simulation delta-cycle. Is this correct?

If it would help to upload my code I can do so.

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Moderator
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143 Views
Registered: ‎04-24-2013

Re: Post-synthesis simulation shows 100ps shift of a signal instead of 1 clock cycle

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Hi @ronnywebers ,

I'm not an AXI expert, but as you are running the Post Synthesis simulation then the tools use the UNISIM Library.

You can find these here: <Vivado_Install_Dir>/data/vhdl/src/unisims

Looking into the primitive defintions you can see that there is a 100 ps delay built in e.g.

constant SYNC_PATH_DELAY : time := 100 ps; in the FIFO18E1.vhd or

constant OUTCLK_DELAY : time := 100 ps; in the DIFFINBUF.vhd

This would explain the 100 ps delay that you are seeing.

Best Regards
Aidan

 

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3 Replies
Moderator
Moderator
144 Views
Registered: ‎04-24-2013

Re: Post-synthesis simulation shows 100ps shift of a signal instead of 1 clock cycle

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Hi @ronnywebers ,

I'm not an AXI expert, but as you are running the Post Synthesis simulation then the tools use the UNISIM Library.

You can find these here: <Vivado_Install_Dir>/data/vhdl/src/unisims

Looking into the primitive defintions you can see that there is a 100 ps delay built in e.g.

constant SYNC_PATH_DELAY : time := 100 ps; in the FIFO18E1.vhd or

constant OUTCLK_DELAY : time := 100 ps; in the DIFFINBUF.vhd

This would explain the 100 ps delay that you are seeing.

Best Regards
Aidan

 

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Give Kudos to a post which you think is helpful and may help other users
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Scholar ronnywebers
Scholar
131 Views
Registered: ‎10-10-2014

Re: Post-synthesis simulation shows 100ps shift of a signal instead of 1 clock cycle

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thanks @amaccre , that suddenly clarifies a lot to me!

So the models used during behavioral simulatoin and post-synthesis functional simulation are different ...? So post-synthesis uses the UNISIM models, are there also models for the behavioral simulation somewhere? I checked the unisim model for the FDRE that outputs the AXI_ARREADY signal in the screenshots, indeed there's also a 100ps output delay in that model!

Are these added to avoid simulation race conditions / delta-cycle issues? I believe ot understand that simulation steps are 1ps, so putting an output delay avoids any delta-cycle issues (?)

If I may ... I created a related post before this one here, in which I see a difference in post-synthesis functional simulation of a custom IP, when I switch between Zynq and Zynq UltraScale+ as target. Because that post is probably too much asked for many people, I created this 2nd post post to understand where the 100ps delay was coming from, so thanks for solving that!

Would you mind dropping an eye on that post, any tip or idea could get me further. I'm just wondering if I'm looking at a simulation 'race condition'.

What is now also kind of strange to me, but might give you a clue in the other post, is that in the screenshots above, in the 'correct' case (first screenshot), there is no 100ps delay after the rising edge on the AXI_ARREADY. In the 'wrong' case (2nd and 3rd screenshot), I do observe the 100ps delay from the unisim model. So I'm now also wondering why I don't see the 100ps delay in the first screenshot ... the FDRE has an OUT_DELAY = 100ps

Fyi, if you ever need to understand AXI a bit better, I found this document very enlightning - I read this first and it was sufficient to understand AXI's 5 channels and signals, as well as basic operation (it's actually rather simple). It's like a 30 minute read or so. After that I could find my way much better in the official ARM AXI specs :-) I actually learned from this document how to build my own custom AXI IP, something that Xilinx offers no tutorial on :-)

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Moderator
Moderator
120 Views
Registered: ‎04-24-2013

Re: Post-synthesis simulation shows 100ps shift of a signal instead of 1 clock cycle

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Hi @ronnywebers ,

Just to clarify, the Behavioural and Post Synthesis simulations both use the same libraries, but in the Behavioural it is parsing the RTL unless you have specifically instantiated primitives.

You can see the libraries used in the table from UG900

Capture1.PNG

Thank you for the AXI document, it looks interesting and I'll work through it.

I'll also look at your previous post and reply from there.

Best Regards
Aidan

 

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