cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
rtfinch
Adventurer
Adventurer
1,090 Views
Registered: ‎01-06-2016

Predefined constant for simulation

Jump to solution

Is there a predefined constant that indicates simulation is running? I'd like to be able to make code dependent on this rather than having to change all the defined SIM constants in multiple files.

 

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
graces
Moderator
Moderator
986 Views
Registered: ‎07-16-2008

Right, it's for simulation.

For synthesis, macro SYNTHESIS is internally 1 in vivado synthesis.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

5 Replies
richardhead
Scholar
Scholar
1,048 Views
Registered: ‎08-01-2012

What sim constants are you referring to? what language? what tool?

0 Kudos
rtfinch
Adventurer
Adventurer
1,042 Views
Registered: ‎01-06-2016

The tool in use is the Vivado 18.3 built in simulator. The language is SystemVerilog. I'm assuming there are some built in constant for which I haven't been able to find documentation on. For instance the C pre-processor has __FILE__ etc.Does SystemVerilog or the simulator have similar constants? I assume the predefined constants would be generic to multiple simulators / languages.

 

0 Kudos
graces
Moderator
Moderator
1,015 Views
Registered: ‎07-16-2008

Below is from UG900.

XILINX_SIMULATOR is a Verilog predefined-macro. The value of this macro is 1.
Predefined macros perform tool-specific functions, or identify which tool to use in a design flow. The following is an example usage:
`ifdef VCS
// VCS specific code
`endif
`ifdef INCA
// NCSIM specific code
`endif
`ifdef MODEL_TECH
// MODELSIM specific code
`endif
`ifdef XILINX_ISIM
// ISE Simulator (ISim) specific code
`endif
`ifdef XILINX_SIMULATOR
// Vivado Simulator (XSim) specific code
`endif

Is this what you're looking for?

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------
0 Kudos
rtfinch
Adventurer
Adventurer
997 Views
Registered: ‎01-06-2016

It may be what I'm looking for.

Is the XILINX_SIMULATOR constant only defined during simulation (and not during synthesis)?

0 Kudos
graces
Moderator
Moderator
987 Views
Registered: ‎07-16-2008

Right, it's for simulation.

For synthesis, macro SYNTHESIS is internally 1 in vivado synthesis.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post