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Visitor cruaud-n
Visitor
116 Views
Registered: ‎05-27-2019

Problem with the value of a register

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Hello,
I use ISE 14.7 (I'm beginner) in order to Chacha20 into FPGA. A register 'start' commands a 'Chacha20' module.


My issue: In my top module (which contain 'Chacha20' module), when my reset is to 1, I put start reg to 0 (first picture / top.v) but when look at simulation (picture 2) 'start' stays to 1 during a long time... It changes of value only when a counter has finished to counting (third picture)

Someone has an idea why I can't command correctly start reg?


Thanks to those who will take the time to help me and sorry for the mistakes.

 

 

`timescale 1ns / 1ps

module top(lbus_clkn, lbus_rstn, gpio_startn, gpio_endn, gpio_exec, led);
// Local bus for GII
   input         lbus_clkn, lbus_rstn;
// GPIO and LED
   output        gpio_startn, gpio_endn, gpio_exec;
   output [7:0]  led;
// Internal variables
   reg start=1; 
   wire done; 
   wire [511:0] out ;
// Internal clock
   wire clk, rst;
	
// Encryption parameters
   parameter N_calculation = 3; // number of out 
   parameter N_test = 3;// number of out checked
   parameter DELAY = 100;
   parameter DELAY_START = 65800;//2^16+250   
	
   reg [4:0] i = 0; //taille de i de N_average
   reg [255:0] keys;
   reg [95:0] nonces;
   reg [31:0] counter;
   reg [511:0] expected_outs [N_test-1:0];
	
   wire[25:0] delay_counter; // counter/delay for wait after each out calculation
   wire[25:0] delay_start; // counter/delay for put start reg to 1 after reset
	
reg rst_counter=1; //Stop/initialize the 'delay' module up_counter reg rst_start=1; //Stop/initialize the 'delay_s' module up_counter // Instantiations MK_CLKRST mk_clkrst (.clkin(lbus_clkn), .rstnin(lbus_rstn), .clk(clk), .rst(rst)); chacha20 encryption_module(.clock(clk), .start(start), .key(keys), .index(counter), .nonce(nonces), .done(done), .out(out)); up_counter delay(.clk(clk), .reset(rst_counter), .counter(delay_counter)); up_counter delay_s(.clk(clk), .reset(rst_start), .counter(delay_start)); assign gpio_startn = !start; initial
begin keys = 256'had0578e5e962fc0a42ffc03175018beeb7ae69dcf1490ca889ac12fdbe8466d3; nonces = 96'hf1d69cbf8e34191d7024af3b; counter = 32'h0; expected_outs[0] = 512'h10ce7542ae81c4481577f3b90dcbc179761492130f76b1ffadd93d7947cea1b962d99a74de90d42085363eb13cf1958376437b3baf1bb01b693a4adc09b2034f; expected_outs[1] = 512'h3610072069e6f9f9e883cb121cc14b41c1b57169f97d9712e1548208b98752d3dcc745e2af430a8ddf54e327689807cbbb6f1ba3ac61c114b9819a408640253e; expected_outs[2] = 512'h64cd8517f5d37e12043c22b70fe8ed52398ec694f56d5814a14b0d16a3279e723d117867af9de92772f704335b3a00e8545c5ad60cd7553f389876adc6424ef0; $display("\n\n----PARAMETERS----\n keys = 256'h%h;\n nonces = 96'h%h;\n", keys,nonces); end always @(posedge clk) begin if (done) begin rst_counter<=0; //Start of 'delay' $display("\nCounter = 32'd%0d;\nOut = 512'h%h;",counter,out); if (counter<=N_test) begin $display(" |CHECK %0d/%0d: 0x%x == 0x%x", N_average*counter+i+1,N_test*N_average, out, expected_outs[counter]); if(out === expected_outs[counter]) begin $display(" |SUCCESS\n"); end else $display(" |FAIL\n"); end else $display(""); if (i < N_average-1) begin i <= i + 1; end if (i == N_average-1) begin counter<=counter+1; i<=0; end if (counter == N_calculation-1 && i == N_average-1) begin i<=N_average; //stop repetition counter<=N_calculation; //stop increment counter rst_counter<=1; //Stop/initialize 'delay' module end end
if (delay_counter>=DELAY) begin rst_counter<=1; //Stop/initialize 'delay' module if(!(counter == N_calculation-1 && i == N_average-1))//while(!end) start <= 1; end
if (delay_start>=DELAY_START) begin start <= 1; rst_start<=1; end
if (rst) begin start <= 0;

rst_start<=0; counter <= 0; i <= 0; rst_counter<=1;//Stop/initialize 'delay' module end
if (start && !rst) //When reset is to 0, if start equal 1, we put it to 0 begin start <= 0; end
end endmodule //============= COUNTER ================= module up_counter(input wire clk, input wire reset, output wire[25:0] counter); reg [25:0] counter_up; // up counter always @(posedge clk or posedge reset) begin if(reset) counter_up <= 26'd0; else counter_up <= counter_up + 26'd1; end assign counter = counter_up; endmodule //============= MK_CLKRST ================= module MK_CLKRST (clkin, rstnin, clk, rst);
//synthesis attribute keep_hierarchy of MK_CLKRST is no; //------------------------------------------------
input clkin, rstnin; output clk, rst; //------------------------------------------------ wire refclk; // wire clk_dcm, locked; //------------------------------------------------ clock IBUFG u10 (.I(clkin), .O(refclk)); /* DCM_BASE u11 (.CLKIN(refclk), .CLKFB(clk), .RST(~rstnin), .CLK0(clk_dcm), .CLKDV(), .CLK90(), .CLK180(), .CLK270(), .CLK2X(), .CLK2X180(), .CLKFX(), .CLKFX180(), .LOCKED(locked)); BUFG u12 (.I(clk_dcm), .O(clk)); */ BUFG u12 (.I(refclk), .O(clk)); //------------------------------------------------ reset MK_RST u20 (.locked(rstnin), .clk(clk), .rst(rst)); endmodule //=============== MK_RST =============== module MK_RST (locked, clk, rst); //synthesis attribute keep_hierarchy of MK_RST is no; //------------------------------------------------ input locked, clk; output rst; //------------------------------------------------ reg [15:0] cnt; //------------------------------------------------ always @(posedge clk or negedge locked) if (~locked) cnt <= 16'h0; else if (~&cnt) cnt <= cnt + 16'h1; assign rst = ~&cnt; endmodule // MK_RST
screen verilog.PNG
simulation start.PNG
delay start.PNG
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Visitor cruaud-n
Visitor
57 Views
Registered: ‎05-27-2019

Re: Problem with the value of a register

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Hello Olupj,

thank you for trying help me. I found a way to workaround.

Sorry for the inconvenience.

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2 Replies
Adventurer
Adventurer
81 Views
Registered: ‎01-27-2008

Re: Problem with the value of a register

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Hi,

I was preparing a lengthy response based on what I *think* I see in your code, but it would be best if:

1. Share your testbench (we can ignore the chacha20 crypto unit)

2. State what your expected behavior is (a bit nebulous to say: " 'start' stays to 1 during a long time... It changes of value only when"). Tell us what you expect the release from reset to do with start.

Thanks.

Jerry

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Visitor cruaud-n
Visitor
58 Views
Registered: ‎05-27-2019

Re: Problem with the value of a register

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Hello Olupj,

thank you for trying help me. I found a way to workaround.

Sorry for the inconvenience.

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