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Explorer
Explorer
1,228 Views
Registered: ‎05-22-2008

Questa Sim design unit not found

I am simulating a design using Questa, and it is erroring out when it looks for the underlying xilinx code for an axis_data fifo that I instantiate using the IP catalog. 

My design has a custom IP wrote, a Xilinx FFT IP i dropped in using IP catalog, a Xilinx CMPY IP I dropped in using IP catalog, the aforementioned axis_data_fifo I dropped in using IP catalog, and a bunch of VHDL I wrote. To get everything working in my questa project I added all my VHDL, I generated output products for all the IPs, I added the myproj/myproj_ip_user_files/<EACH_IP>/sim/instance_name.vhd files for each IP. It is in these files that the named instances in my top level design get mapped to the lower lever xilinx primitives or macros or whatever magic xilinx does.

Below is the error:

 

# Loading work.inferred_rom(rtl)
# Loading work.cmpy_0(cmpy_0_arch)
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/cmpy_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/cmpy_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# Refreshing /home/vuser/work.axis_data_fifo_32_x16
# Loading work.axis_data_fifo_32_x16
# ** Error: (vsim-3033) /data/mckinneyj/project_sbt/project_sbt.ip_user_files/ip/axis_data_fifo_32_x16/sim/axis_data_fifo_32_x16.v(112): Instantiation of 'axis_data_fifo_v1_1_17_axis_data_fifo' failed. The design unit was not found.
#    Time: 0 fs  Iteration: 0  Instance: /os_sbt_tb/os_sbt_inst/fifo_instance File: /data/mckinneyj/project_sbt/project_sbt.ip_user_files/ip/axis_data_fifo_32_x16/sim/axis_data_fifo_32_x16.v
#         Searched libraries:
#             /home/vuser/work

 But If I look in the Questa library window said design unit is there:

questa_cap_cropped.png

   What Am I doing wrong?

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4 Replies
Xilinx Employee
Xilinx Employee
1,202 Views
Registered: ‎07-16-2008

回复: Questa Sim design unit not found

Did you specify '-L axis_data_fifo_v1_1_17' in the vsim command?

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Explorer
Explorer
1,186 Views
Registered: ‎05-22-2008

回复: Questa Sim design unit not found

No, I hadn't. I primarily use the buttons on the GUI. In the Questasim TCL/command window it appears that the command executed is "vsim -novopt worl.os_ont_tb(testbed)

I just tried though I get related but different errors

vsim -novopt work.os_sbt_tb(testbed) -L axis_data_fifo_v1_1_17
# vsim -novopt work.os_sbt_tb(testbed) -L axis_data_fifo_v1_1_17 
# Start time: 08:33:07 on Nov 30,2018
# ** Warning: (vsim-8891) All optimizations are turned off because the -novopt switch is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features please see the User's Manual section on Preserving Object Visibility with vopt.
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.std_logic_textio(body)
# Loading work.os_sbt_tb(testbed)
# Loading work.m_axis_tb(testbed)
# Loading work.os_sbt(structural)
# Loading work.overlap_inputs_axis_0(overlap_inputs_axis_0_arch)
# Loading work.overlap_inputs_axis_v1_0(arch_imp)
# Loading work.overlap_inputs_axis_v1_0_s00_axis(arch_imp)
# Loading work.overlap_input(beh)
# Loading work.overlap_inputs_axis_v1_0_m00_axis(implementation)
# Loading work.xfft_0(xfft_0_arch)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading ieee.math_real(body)
# Loading ieee.std_logic_signed(body)
# Loading unisim.muxcy(muxcy_v)
# Loading unisim.xorcy(xorcy_v)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.fdre(fdre_v)
# Loading unisim.fdse(fdse_v)
# Loading unisim.lut6(lut6_v)
# Loading unisim.fde(fde_v)
# Loading unisim.lut3(lut3_v)
# Loading unisim.srl16e(srl16e_v)
# Loading unisim.fdr(fdr_v)
# Loading unisim.fd(fd_v)
# Loading unisim.lut4(lut4_v)
# Loading unisim.ramb18(ramb18_v)
# Loading unisim.ramb18e1(ramb18e1_v)
# Loading unisim.rb18_internal_vhdl(rb18_internal_vhdl_v)
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/fft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 2 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/fft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# Loading unisim.dsp48e2(dsp48e2_v)
# Loading unisim.vcc(vcc_v)
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/fft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 2 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/fft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/fft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 2 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/fft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# Loading unisim.srlc32e(srlc32e_v)
# Loading unisim.lut1(lut1_v)
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/fft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 2 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/fft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/fft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 2 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/fft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# Loading unisim.muxf7(muxf7_v)
# Loading unisim.muxf8(muxf8_v)
# Loading work.inferred_rom(rtl)
# Loading work.cmpy_0(cmpy_0_arch)
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/cmpy_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/cmpy_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# Loading work.axis_data_fifo_32_x16
# Refreshing /data/mckinneyj/project_sbt/project_sbt.cache/compile_simlib/questa/axis_data_fifo_v1_1_17.axis_data_fifo_v1_1_17_axis_data_fifo
# Loading axis_data_fifo_v1_1_17.axis_data_fifo_v1_1_17_axis_data_fifo
# ** Error: (vsim-3033) /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/axis_data_fifo_v1_1/hdl/axis_data_fifo_v1_1_vl_rfs.v(590): Instantiation of 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' failed. The design unit was not found.
#    Time: 0 fs  Iteration: 0  Region: /os_sbt_tb/os_sbt_inst/fifo_instance/inst/gen_fifo_generator File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/axis_data_fifo_v1_1/hdl/axis_data_fifo_v1_1_vl_rfs.v
#         Searched libraries:
#             /data/mckinneyj/project_sbt/project_sbt.cache/compile_simlib/questa/axis_data_fifo_v1_1_17
#             /home/vuser/work
# ** Error: (vsim-3033) /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/axis_data_fifo_v1_1/hdl/axis_data_fifo_v1_1_vl_rfs.v(819): Instantiation of 'fifo_generator_v13_2_2' failed. The design unit was not found.
#    Time: 0 fs  Iteration: 0  Region: /os_sbt_tb/os_sbt_inst/fifo_instance/inst/gen_fifo_generator File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/axis_data_fifo_v1_1/hdl/axis_data_fifo_v1_1_vl_rfs.v
#         Searched libraries:
#             /data/mckinneyj/project_sbt/project_sbt.cache/compile_simlib/questa/axis_data_fifo_v1_1_17
#             /home/vuser/work
# ** Error: (vsim-3033) /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/axis_data_fifo_v1_1/hdl/axis_data_fifo_v1_1_vl_rfs.v(1061): Instantiation of 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' failed. The design unit was not found.
#    Time: 0 fs  Iteration: 0  Region: /os_sbt_tb/os_sbt_inst/fifo_instance/inst/gen_fifo_generator File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/axis_data_fifo_v1_1/hdl/axis_data_fifo_v1_1_vl_rfs.v
#         Searched libraries:
#             /data/mckinneyj/project_sbt/project_sbt.cache/compile_simlib/questa/axis_data_fifo_v1_1_17
#             /home/vuser/work
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/ifft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 2 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/ifft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/ifft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 2 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/ifft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/ifft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 2 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/ifft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/ifft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 2 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/ifft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult1 pps: a b extra_b  1 1 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/ifft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# ** Note: mult2 pps: a b extra_b  1 2 0
#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/ifft_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# Loading work.discard_samples_axis(beh)
# Loading work.discard_samples(beh)
# Error loading design
# End time: 08:33:08 on Nov 30,2018, Elapsed time: 0:00:01
# Errors: 3, Warnings: 1

There are no errors for the xfft or the cmpy IPs and I don't on the command line specify the library for each of those. So I wonder why I need to specify the library for the fifo? Looking at the questa gui's library listing, xfft_0 and cmpy_0 are listed as "entity", while axis_data_fifo is listed as "module" 

Looking at the new errors above, each of those components exist in the Library listing in the questa gui, in the same way the axis_data_fifo is listed, so I might be able to add them with a "-L <design_unit> , so I am going to try that, but I am reluctant to believe that, even if this approach works, it's the "right" solution

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Explorer
Explorer
1,180 Views
Registered: ‎05-22-2008

回复: Questa Sim design unit not found

I found in the gui where one adds libraries, and added the axis_infrastructure library and now my errors are:

#    Time: 0 fs  Iteration: 0  Protected: /os_sbt_tb/os_sbt_inst/cmpy_inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/cmpy_v6_0/hdl/cmpy_v6_0_vh_rfs.vhd
# Loading work.axis_data_fifo_32_x16
# Loading axis_data_fifo_v1_1_17.axis_data_fifo_v1_1_17_axis_data_fifo
# Refreshing /data/mckinneyj/project_sbt/project_sbt.cache/compile_simlib/questa/axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper
# Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper
# Refreshing /data/mckinneyj/project_sbt/project_sbt.cache/compile_simlib/questa/axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector
# Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector
# Refreshing /data/mckinneyj/project_sbt/project_sbt.cache/compile_simlib/questa/axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis
# Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis
# ** Error: (vsim-3033) /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/axis_data_fifo_v1_1/hdl/axis_data_fifo_v1_1_vl_rfs.v(819): Instantiation of 'fifo_generator_v13_2_2' failed. The design unit was not found.
#    Time: 0 fs  Iteration: 0  Region: /os_sbt_tb/os_sbt_inst/fifo_instance/inst/gen_fifo_generator File: /opt/Xilinx/Vivado/2018.1/data/ip/xilinx/axis_data_fifo_v1_1/hdl/axis_data_fifo_v1_1_vl_rfs.v
#         Searched libraries:
#             /data/mckinneyj/project_sbt/project_sbt.cache/compile_simlib/questa/axis_data_fifo_v1_1_17
#             /data/mckinneyj/project_sbt/project_sbt.cache/compile_simlib/questa/axis_infrastructure_v1_1_0
#             /home/vuser/work

I subsequently went and added fifo_generator_13_2_2 and the simulation is no longer erroring out, so that is awesome, I haven't verfied that it's working yet.

I'd still like to know how it knows to find the xfft and cmpy with my help, but not the axis_*** stuff. The axis_...stuff is verilog, where everything else seems to be vhdl. I wonder if there is/what a difference in the way verilog and VHDL map components to entities, or entities to architectures.

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Xilinx Employee
Xilinx Employee
1,150 Views
Registered: ‎07-16-2008

回复: Questa Sim design unit not found

If you were launching modelsim simulation from the GUI, the requried libraries should have been added correctly to the vopt command (the tool auto-generated 3-step script).

All you have to do is to specify the pre-compiled library location in the simulation setting.

If you create your own simulation script and run in Modelsim standalone, you need to ensure all IP simulation files were compiled and the correct libraries were loaded. You can export a simulation script for the current project by doing File > Export > Export Simulation.

 

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