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Adventurer
Adventurer
205 Views
Registered: ‎05-16-2014

QuestaSim Not Displaying All Signals

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Questa Sim -84 10.6c

I have a simple VHDL project. A TOP level, a CORE, and a few other entities. Also, a testbench. The testbench instantiates the DUT (top level). The DUT instantiates the CORE. The CORE instantiates the other entities. The DUT (top level)  signals are OK. When i highlight the CORE in QuestaSim's Instance window not all of the CORE's input and output signals are being displayed in the Object window. I checked the OBJECTS -> Show and everything is checked. Also, if I highlight any of the other entities the clocks and reset input signals are not being displayed as well as some other input & output signals.

If I just simulate the CORE then all of the CORE's signals are displayed so I know they're there.

Anyone know what's wrong?

 

Thanks,

Swimteam

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Xilinx Employee
Xilinx Employee
161 Views
Registered: ‎07-16-2008

回复: QuestaSim Not Displaying All Signals

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I think that's due to the optimization performed by Questasim.

If you want to disable the optimization and view more signals, try to start simulation with '-novopt'.

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Xilinx Employee
Xilinx Employee
162 Views
Registered: ‎07-16-2008

回复: QuestaSim Not Displaying All Signals

Jump to solution

I think that's due to the optimization performed by Questasim.

If you want to disable the optimization and view more signals, try to start simulation with '-novopt'.

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Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos