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Voyager
Voyager
1,944 Views
Registered: ‎02-10-2012

Question on Timing simulation in Zynq

I can get the behavioral simulation to work correctly in my design . Now I am working on getting the timing simulation up and running. I read in one of the manuals from Xilinx that SIMPRIM library ( which is required when one has to do a timing simulation ) is only in Verilog!

 

So my question is : If I have a VHDL test bench will it compile ? My entire design in in VHDL . Will I be able to perform a post timing simulation ?

 

Regards

Arvind

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