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Adventurer
Adventurer
1,029 Views
Registered: ‎02-12-2018

RTL vs GLS Mismatch

Hi,

 

I have attached a very simple 8-bit counter testcase, for doing timing simulation, on the GUI.
I am seeing a difference in RTL vs GLS simulation, where the post-P&R timing netlist increments only after more than 30 clock cycles after the reset is deasserted.
Why is the counter not incrementing from the next clock cycle after the reset is disabled, in timing simulation?

 

Clock Period : 2.35 ns
Tool Version: Vivado v.2017.2.1 (win64)

Device : Zynq UltraScale+

 

Thanks

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2 Replies
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Scholar
Scholar
1,021 Views
Registered: ‎09-16-2009

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Moderator
Moderator
982 Views
Registered: ‎05-31-2017

Hi @xilinxmax,

 

In support to @markcurry comments, this is because of the GSR signal 

GSR.JPG

Please check page 13 of UG 900 regarding this.

 

Thanks & Regards,
A.Shameer

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