02-27-2018 12:25 PM
I have attached a very simple 8-bit counter testcase, for doing timing simulation, on the GUI.
I am seeing a difference in RTL vs GLS simulation, where the post-P&R timing netlist increments only after more than 30 clock cycles after the reset is deasserted.
Why is the counter not incrementing from the next clock cycle after the reset is disabled, in timing simulation?
Clock Period : 2.35 ns
Tool Version: Vivado v.2017.2.1 (win64)
Device : Zynq UltraScale+
02-27-2018 12:37 PM
Probably GSR simulation issues.
02-27-2018 08:11 PM