Vivado Simulation

[cforte@naii.com]

Is the testbench template available yet?

[graces]

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cforte@naii.com wrote:

Is the testbench template available yet?

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The built-in feature is still on the roadmap. However, user can make use of the powerful capabilities of Tcl to create their own script to fulfill specific requirement. In 2014.1 (released tomorrow), Xilinx Tcl Store is introduced, which is an open source repository for sharing useful Tcl scripts. 

Attached is an example script to create an instantiation template of a module in testbench. To use the script,

1. Within Vivado GUI, select Tools > Run Tcl Scripts and browse to create_verilog_template.tcl
2. In Tcl Console, run the following command.
create_top input_top_level.v testbench.v

[debrajr]

Making this as a new topic as other visitors may be interested.

[bassman59]

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cforte@naii.com wrote:

Is the testbench template available yet?

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emacs has a nifty test bench generation feature. It instantiates your DUT, creates signals to map to that DUT, and makes a clock generator. You can easily edit the template.

Of course, the test bench is a whole lot more than the DUT and a clock. You need to instantiate models of your data sources and sinks, add assertions for checks on DUT output vs expected output, etc etc.