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Observer
Observer
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Registered: ‎04-27-2017

Removing debug port changes functionality on post-implementation timing simulation

Hello,

I am trying to implement SHA256 hash core. My design works properly and has computed true results on all kind of simulations. But in that design I have a debug port at top module and it is connected to an inter-modules signal. When I remove that port on top module, the design works on behavioral and post-implementation functional simulation properly but post-implementation timing simulation has faulty results at the output. The design passes timing analysis all the time. 

 

Is there a way or a guide to apply on these situations to solve the problem? 

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