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azonenberg
Visitor
Visitor
1,952 Views
Registered: ‎06-12-2012

Reproducible segfault in XSIM with malformed function call

Steps to reproduce:

  • Open Vivado 2017.3
  • Create a new project with default settings
  • Add a single simulation source containing the following code:
    `timescale 1ns / 1ps
    module test();
    
    	function integer foo;
    		input integer i;
    		case(i)
    			0:	foo = 1;
    			default: foo = 2;
    		endcase
    	endfunction
    	
    	initial begin
    		$display("foo = %d", foo[0]);
    	end
    
    endmodule
  • Run a behavioral simulation

Expected result: xvlog fails with a syntax error clearly marking the offending line and describing the error (use of square brackets instead of parentheses for the function call)

 

Actual result: xsim crashes without an error message clearly indicating the problem. Elaborate.log contains the following:

Vivado Simulator 2017.3
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2017.3/bin/unwrapped/lnx64.o/xelab -wto 6ff47ac2f2194d82b2869350d1b79130 --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot test_behav xil_defaultlib.test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
ERROR: [XSIM 43-3316] Signal SIGSEGV received.

 

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6 Replies
sunilku
Xilinx Employee
Xilinx Employee
1,909 Views
Registered: ‎08-10-2015

hi @azonenberg,

 

This is bug in Vivado Simulator. Issue reported to factory.

 

Thanks,

Sunilkumar

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thakurr
Moderator
Moderator
1,892 Views
Registered: ‎09-15-2016

Hi @azonenberg

 

Which OS you are using? The crash is not reproducible on my machine. At my end : xvlog fails with a syntax error clearly marking the offending line and describing the error. Attach is the xvlog.log

Yes, such crash issue during elaboration has been reported earlier with different use cases and which is slated to be fixed in future releases. 

Can you try the workaround mention in the below AR:

https://www.xilinx.com/support/answers/69251.html

 

Regards

Rohit

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Rohit
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azonenberg
Visitor
Visitor
1,877 Views
Registered: ‎06-12-2012

I'm testing on 64-bit Linux (Debian stable) with Vivado 2017.3.

The workaround in the linked AR did not solve the problem.

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thakurr
Moderator
Moderator
1,869 Views
Registered: ‎09-15-2016

@azonenberg

 

This is not a supported OS with Xilinx tool. Hence you can see such indeterministic results which you can see at your end and which i cannot see. I suggest you to use supported OS with Vivado 2017.3. Here is the link, page 16 for all supported OS for 2017.3:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug973-vivado-release-notes-install-license.pdf

 

I believe it will help you.

 

Regards

Rohit

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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----------------------------------------------------------------------------------------------

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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elaforest
Visitor
Visitor
1,801 Views
Registered: ‎05-08-2017

Tested on Ubuntu 16.04.3 LTS, and I see the bug.

Xsim segfaults on what should be a syntax error.

Thus the bug is not specific to Debian.

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azonenberg
Visitor
Visitor
1,784 Views
Registered: ‎06-12-2012

Here's a backtrace which might be of use to the developers:

(gdb) bt
#0  0x0000000000595b03 in ISIMC::VlogTreeTransform::handleDefValOfArgs(Verific::VeriIdDef*, Verific::Array*, ISIMC::MoveExprToUpperScope*, Verific::VeriTreeNode*) ()
#1  0x00000000005c6bc7 in ISIMC::VlogTreeTransform::Visit(Verific::VeriFunctionCall&) ()
#2  0x00000000005c2618 in ISIMC::VlogTreeTransform::Visit(Verific::VeriIdRef&) ()
#3  0x00007ffff4e93481 in Verific::VeriVisitor::Visit(Verific::VeriIndexedId&) () from /opt/xilinx/Vivado/2017.3/lib/lnx64.o/libxsimverific.so
#4  0x00000000005bd987 in ISIMC::VlogTreeTransform::Visit(Verific::VeriIndexedId&) ()
#5  0x00007ffff4e8e566 in Verific::VeriVisitor::TraverseArray(Verific::Array const*) () from /opt/xilinx/Vivado/2017.3/lib/lnx64.o/libxsimverific.so
#6  0x00007ffff4e98528 in Verific::VeriVisitor::Visit(Verific::VeriSystemTaskEnable&) () from /opt/xilinx/Vivado/2017.3/lib/lnx64.o/libxsimverific.so
#7  0x00000000005d5781 in ISIMC::VlogTreeTransform::Visit(Verific::VeriSystemTaskEnable&) ()
#8  0x00007ffff4e8e566 in Verific::VeriVisitor::TraverseArray(Verific::Array const*) () from /opt/xilinx/Vivado/2017.3/lib/lnx64.o/libxsimverific.so
#9  0x00007ffff4e946c8 in Verific::VeriVisitor::Visit(Verific::VeriSeqBlock&) () from /opt/xilinx/Vivado/2017.3/lib/lnx64.o/libxsimverific.so
#10 0x00000000005bbebd in ISIMC::VlogTreeTransform::Visit(Verific::VeriSeqBlock&) ()
#11 0x00007ffff4e90e39 in Verific::VeriVisitor::Visit(Verific::VeriInitialConstruct&) () from /opt/xilinx/Vivado/2017.3/lib/lnx64.o/libxsimverific.so
#12 0x00000000005b5848 in ISIMC::VlogTreeTransform::Visit(Verific::VeriInitialConstruct&) ()
#13 0x00007ffff4e8e566 in Verific::VeriVisitor::TraverseArray(Verific::Array const*) () from /opt/xilinx/Vivado/2017.3/lib/lnx64.o/libxsimverific.so
#14 0x00007ffff4e952e8 in Verific::VeriVisitor::Visit(Verific::VeriModule&) () from /opt/xilinx/Vivado/2017.3/lib/lnx64.o/libxsimverific.so
#15 0x00000000005e107b in ISIMC::VlogTreeTransform::Visit(Verific::VeriModule&) ()
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