UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Scholar samcossais
Scholar
9,267 Views
Registered: ‎12-07-2009

SRIO Gen2 netlist models slow, behavioral models (encrypted) generate errors

Jump to solution

Hi

 

I am simulating a system including an SRIO Gen2 x4 @5Gbps link and I found the simulation very slow compared to other simulations I did in the past with the same kind of links (PCIe Gen2 @5Gbps , SRIO Gen1 @2.5G).

 

For the first time I work with Vivado for this project, but the simulation itself is done with Modelsim, and I made a separate Modelsim project for that (I don't run sim from Vivado).

 

- PC and software environment: Intel core i7 3870, Windows 7 64b 32GB RAM, Modelsim SE 10.3 64b, Vidado 2013.3 64b

- Simulation libraries compiled with Vivado tcl command "compile_simlib"

- Target devices : 2 Kintex-7

- Notable IPs used : SRIO Gen2 v3.0, Aurora v10.0, FIFO Generator v11.0, BRAM Generator v8.0, Distributed RAM Generator v8.0

 

As I said I used to simulate similar systems containing similar high speed links, including a SRIO Gen1 x4 @2.5Gbps and PCIe 2.0 @5Gbps. This time simulation runtime is significantly slower and this will be an issue for my further simulation tests of my complex system.

 

After some research, I was able to find which files were supposed to be the post-synthesis structural/netlist model of the SRIO IP and which files were supposed to be the behavioral model. Simulation works when I use the netlist model, but it is very slow and my experience led me to think it was because the SRIO model was not the behavioral one. However, as mentionned in the title, the behavioral model is encrypted (both VHDL and Verilog encrypted files) and generates errors when I compile it.

 

Do you have any way to make my simulation faster ?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar samcossais
Scholar
14,109 Views
Registered: ‎12-07-2009

Re: SRIO Gen2 netlist models slow, behavioral models (encrypted) generate errors

Jump to solution

I also recompiled the FPGA primitives libraries (unisims, simprims unifast and secureip) using the options above (in particular -nodebug) and adding [_no_debug] to their name.

 

I set the library first priority to unifast (vsim -L unifast_ver_nodebug -L unisims_ver_nodebug).

 

I added a config.v file to force the use of the unisims_ver_nodebug library for the FIFO model as the First Word Fall Through mode is not supported by the unifast model (if the warning I get is correct).

 

Concerning the config.v file, you explain its use in the ug900 user guide and I followed your advice :


config cfg_sim_top;
    design work.sim_top;
    // FIFO FWFT mode not supported by the unifast model, force the use of the unisims one.
    cell FF18_INTERNAL_VLOG    use unisims_ver_nodbg.FF18_INTERNAL_VLOG;
    cell FF36_INTERNAL_VLOG    use unisims_ver_nodbg.FF36_INTERNAL_VLOG;
endconfig


 

 

But there was nothing on how to actually make the configuration take effect. I think you should add a line about that, such as :


Load the configuration (cfg_sim_top) instead of your simulation top file (sim_top) :
vsim -L fifo_generator_v11_0  -L fifo_generator_v10_0 \
          -L dist_mem_gen_v8_0 -L blk_mem_gen_v8_0 -L srio_gen2_v3_0 \
          -L unifast_ver_nodbg -L unisims_ver_nodbg -L secureip_nodbg -L xilinxcorelib_ver_nodbg work.glbl \
        work.sim_top work.cfg_sim_top


 

0 Kudos
5 Replies
Scholar samcossais
Scholar
9,263 Views
Registered: ‎12-07-2009

Re: SRIO Gen2 netlist models slow, behavioral models (encrypted) generate errors

Jump to solution

Here is the command used to compile the Verilog netlist of the SRIO Gen2 IP :

vlog -work work -O5 \
../../xilinx_prj_rx0_vvd_2013/xilinx_prj_rx0_vvd_2013.srcs/sources_1/ip/srio_gen2_core/srio_gen2_core_funcsim.v

 

And here are commands used to compile the encrypted VHDL and Verilog that I assume to be the behavioral version :
vcom-work work -O5 \
../../xilinx_prj_rx0_vvd_2013/xilinx_prj_rx0_vvd_2013.srcs/sources_1/ip/srio_gen2_core/srio_gen2_v3_0/*.vhd
vlog -work work -O5 \

../../xilinx_prj_rx0_vvd_2013/xilinx_prj_rx0_vvd_2013.srcs/sources_1/ip/srio_gen2_core/srio_gen2_v3_0/*/*.v

 

As I said, when I use these encrypted files instead, I get errors but no details can be given (as the file is encrypted) :

# vsim -L unisims_ver -L secureip -L xilinxcorelib_ver -voptargs=""+acc"" -quiet work.sim_top work.glbl
# Start time: 23:02:12 on Mar 24,2014
# ** Note: (vsim-3812) Design is being optimized...

# ** Error: nofile(53): in protected region

# ** Error: nofile(53): in protected region

( + about 20 times the above error message)

# Optimization failed
# Error loading design
# Error: Error loading design
#        Pausing macro execution

 

Are these files supposed to work in simulation and,

- if yes, how do you make them work ?

- if no, is there another way to make the simulation faster ?

0 Kudos
Scholar samcossais
Scholar
9,260 Views
Registered: ‎12-07-2009

Re: SRIO Gen2 netlist models slow, behavioral models (encrypted) generate errors

Jump to solution
0 Kudos
Scholar samcossais
Scholar
9,248 Views
Registered: ‎12-07-2009

Re: SRIO Gen2 netlist models slow, behavioral models (encrypted) generate errors

Jump to solution

I just found that maybe I should use the unifast library as mentionned in ug900.

I am going to try this tomorrow and see how it speeds up my simulation.

0 Kudos
Scholar samcossais
Scholar
9,207 Views
Registered: ‎12-07-2009

Re: SRIO Gen2 netlist models slow, behavioral models (encrypted) generate errors

Jump to solution

I was able to compile the behavioral model the same way I did here with FIFO Generator :

http://forums.xilinx.com/t5/New-Users-Forum/Simulation-of-fifo-generator-v10/m-p/433952#M9112

 

I also enabled some optimizations for vcom / vlog :


vcom  -work srio_gen2_v3_0 -O5 -64 -nodebug  \

../../xilinx_prj_rx0_vvd_2013/xilinx_prj_rx0_vvd_2013.srcs/sources_1/ip/srio_gen2_core/srio_gen2_v3_0/*.vhd

 

vlog  -work srio_gen2_v3_0 -O5 +nospecify +notimingchecks -nodebug  \

../../xilinx_prj_rx0_vvd_2013/xilinx_prj_rx0_vvd_2013.srcs/sources_1/ip/srio_gen2_core/srio_gen2_v3_0/*/*.v  \

../../xilinx_prj_rx0_vvd_2013/xilinx_prj_rx0_vvd_2013.srcs/sources_1/ip/srio_gen2_core/srio_gen2_v3_0/*/*/*.v


 

The library name MUST be unchanged. Else you get an error and because the file is encrypted, this was really painful to find out... Xilinx IP core models being dependant to their library name is definitely NOT a good practice in my opinion...

0 Kudos
Highlighted
Scholar samcossais
Scholar
14,110 Views
Registered: ‎12-07-2009

Re: SRIO Gen2 netlist models slow, behavioral models (encrypted) generate errors

Jump to solution

I also recompiled the FPGA primitives libraries (unisims, simprims unifast and secureip) using the options above (in particular -nodebug) and adding [_no_debug] to their name.

 

I set the library first priority to unifast (vsim -L unifast_ver_nodebug -L unisims_ver_nodebug).

 

I added a config.v file to force the use of the unisims_ver_nodebug library for the FIFO model as the First Word Fall Through mode is not supported by the unifast model (if the warning I get is correct).

 

Concerning the config.v file, you explain its use in the ug900 user guide and I followed your advice :


config cfg_sim_top;
    design work.sim_top;
    // FIFO FWFT mode not supported by the unifast model, force the use of the unisims one.
    cell FF18_INTERNAL_VLOG    use unisims_ver_nodbg.FF18_INTERNAL_VLOG;
    cell FF36_INTERNAL_VLOG    use unisims_ver_nodbg.FF36_INTERNAL_VLOG;
endconfig


 

 

But there was nothing on how to actually make the configuration take effect. I think you should add a line about that, such as :


Load the configuration (cfg_sim_top) instead of your simulation top file (sim_top) :
vsim -L fifo_generator_v11_0  -L fifo_generator_v10_0 \
          -L dist_mem_gen_v8_0 -L blk_mem_gen_v8_0 -L srio_gen2_v3_0 \
          -L unifast_ver_nodbg -L unisims_ver_nodbg -L secureip_nodbg -L xilinxcorelib_ver_nodbg work.glbl \
        work.sim_top work.cfg_sim_top


 

0 Kudos