STARTUPE2 instantiation causes IDELAY2 simulation to fail
In simulation, the global GSR signal is pulsed active at time 0 in the glbl() module for 100 ns, but only to a weak1. If a STARTUPE2 module is instantiated in the design with its GSR input tied low (to disable it) it over-rides the weak1 pulse value and prevents GSR from transitioning. This causes a simulation problem in IDELAYE2 primitives in configurations which count on a transition of gsr_in to initialize the idelay_count value. The external result is that IDELAYE2 DATAOUT remains low and does not follow IDATAIN.
This can be worked around in the test bench by forcing GSR to a 1 for 100 ns (typically at time 0) and then releasing it.
force glbl.GSR = 1;
#100000 release glbl.GSR; // release GSR after 100 ns