01-15-2016 12:38 AM
I have tried running post-synthesis and post-implementation simulations on a few different design runs, and found that it is absolutely identical to my behavioral simulation. All of the signal names are the same in the simulator, even though when exploring the synthesized and implemented design netlists, I see drastic changes in the hierarchy: net renaming, net removal, etc.
Also, the timing simulations do not show any timing delay whatsoever. My design sources are in VHDL, but from what I understand this should not prevent me from running timing simulation with the simulator language set to 'mixed'.
My testbench simply generates a clock, instantiates the design, and passes it the clock. Do I need to do something else to get a genuine post-synthesis / post-implementation simulation?
01-15-2016 02:04 AM
01-15-2016 12:17 PM
Sorry I forgot to mention that. I am using Vivado 2015.4. After completing a synthesis or implementation run, I first open the synthesized or implemented design. Then I click 'Run Simulation' in the simulation tab of the Flow Navigator. In the menu that pops up I select one of "Run Post-Synthesis Functional Simulation," "Run Post-Synthesis Timing Simulation," etc.
The file I have attached shows some of the tcl commands and results when following this procedure.
Thanks for looking into this!